AD9739BBCZRL Analog Devices Inc, AD9739BBCZRL Datasheet - Page 27

• Manufacturer Part Number: AD9739BBCZRL
• Description: 14 Bit 2.5 GSPS DAC
• Manufacturer: Analog Devices Inc

Specifications of AD9739BBCZRL

• Number Of Bits: 14
• Data Interface: Serial
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 980mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 160-CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Settling Time: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SPI REGISTER MAP
Table 7.
Name
Mode
Power-
Down
CNT_CLK_
Dis
IRQ_En
IRQ_Req
RSVD
FSC_1
FSC_2
Dec_CNT
RSVD
LVDS_CNT
DIG_STAT
LVDS_
STAT1
LVDS_
STAT2
RSVD
RSVD
LVDS_
REC_CNT1
LVDS_
REC_CNT2
LVDS_
REC_CNT3
LVDS_
REC_CNT4
LVDS_
REC_CNT5
LVDS_
REC_CNT6
LVDS_
REC_CNT7
LVDS_
REC_CNT8
LVDS_
REC_CNT9
LVDS_
REC_STAT1
LVDS_
REC_STAT2
LVDS_
REC_STAT3
LVDS_
REC_STAT4
LVDS_
REC_STAT5
LVDS_
REC_STAT6
Address
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
Bit 7
SDIO_DIR
N/A
N/A
N/A
N/A
N/A
FSC[7]
Sleep
N/A
N/A
N/A
HNDOFF_
Fall[3]
SUP/HLD_
Edge1
SUP/HLD_
SYNC
N/A
N/A
SYNC_
FLG_RST
SMP_DEL
[1]
SMP_DEL
[9]
DCI_DEL[3]
CLKDIVPH
[1]
SYNC_
GAIN[1]
N/A
SYNCSH_
DEL[0]
SYNCSH_
DEL[8]
SMP_DEL
[1]
SMP_DEL
[9]
DCI_DEL[1]
DCI_DEL[9]
FINE_DEL_
PST[3]
N/A
Bit 6
LSB/MSB
N/A
N/A
N/A
N/A
N/A
FSC[6]
N/A
N/A
N/A
N/A
HNDOFF_
Fall[2]
N/A
SUP/HLD_
Edge0
N/A
N/A
SYNC_
LOOP_ON
SMP_DEL
[0]
SMP_DEL
[8]
DCI_DEL[2]
CLKDIVPH
[0]
SYNC_
GAIN[0]
SYNCO_
DEL[6]
N/A
SYNCSH_
DEL[7]
SMP_DEL
[0]
SMP_DEL
[8]
DCI_DEL[0]
DCI_DEL[8]
FINE_DEL_
PST[2]
SYNCO_
DEL[6]
Bit 5
Reset
LVDS_DCO
_PD
N/A
SYNC_LST
_EN
SYNC_LST
_IRQ
N/A
FSC[5]
N/A
N/A
N/A
N/A
HNDOFF_
Fall[1]
DCI_PHS3
SYNC_
SAMP1
N/A
N/A
SYNC_
MST/SLV
FINE_DEL_
MID[3]
SMP_DEL
[7]
DCI_DEL[1]
DCI_DEL[9]
SYNCOUT_
PH[1]
SYNCO_
DEL[5]
N/A
SYNCSH_
DEL[6]
N/A
SMP_DEL
[7]
N/A
DCI_DEL[7]
FINE_DEL_
PST[1]
SYNCO_
DEL[5]
Rev. 0 | Page 27 of 56
Bit 4
N/A
LVDS_RCVR
_PD
N/A
SYNC_LCK
_EN
SYNC_LCK
_IRQ
N/A
FSC[4]
N/A
N/A
N/A
N/A
HNDOFF_
Fall[0]
DCI_PHS1
SYNC_
SAMP0
N/A
N/A
SYNC_
CNT_ENA
FINE_DEL_
MID[2]
SMP_DEL
[6]
DCI_DEL[0]
DCI_DEL[8]
SYNCOUT_
PH[0]
SYNCO_
DEL[4]
N/A
SYNCSH_
DEL[5]
N/A
SMP_DEL
[6]
N/A
DCI_DEL[6]
FINE_DEL_
PST[0]
SYNCO_
DEL[4]
Bit 3
N/A
N/A
CLKGEN
_PD
MULST_EN
MULST
_IRQ
N/A
FSC[3]
N/A
N/A
N/A
HNDOFF_
CHK_RST
HNDOFF_
Rise[3]
DCI_PRE
_PH2
LVDS1_HI
N/A
N/A
N/A
FINE_DEL_
MID[1]
SMP_DEL
[5]
FINE_DEL_
SKW[3]
DCI_DEL[7]
LCKTHR[3]
SYNCO_
DEL[3]
N/A
SYNCSH_
DEL[4]
SMP_FINE_
DEL[3]
SMP_DEL
[5]
SYNCOUT
PH[1]
DCI_DEL[5]
FINE_DEL_
PRE[3]
SYNCO_
DEL[3]
Bit 2
N/A
N/A
N/A
MULCK_EN
MULCK
_IRQ
N/A
FSC[2]
N/A
N/A
N/A
N/A
HNDOFF_
Rise[2]
DCI_PRE
_PH0
LVDS1_LO
N/A
N/A
RCVR_FLG
_RST
FINE_DEL_
MID[0]
SMP_DEL
[4]
FINE_DEL_
SKW[2]
DCI_DEL[6]
LCKTHR[2]
SYNCO_
DEL[2]
N/A
SYNCSH_
DEL[3]
SMP_FINE
_DEL[2]
SMP_DEL
[4]
SYNCOUT
PH[0]
DCI_DEL[4]
FINE_DEL_
PRE[2]
SYNCO_
DEL[2]
Bit 1
CLK_REC_
REC_CNT_
CLK
RCV_
N/A
DAC_DEC
N/A
LVDS_
Bias[1]
HNDOFF_
Rise[1]
DCI_PST
_PH2
N/A
N/A
RCVR_
LOOP_ON
RCVR_
GAIN[1]
SMP_DEL
[3]
FINE_DEL_
SKW[1]
LCKTHR[1]
SYNCO_
DEL[1]
N/A
SYNCSH_
DEL[2]
SMP_FINE_
DEL[1]
SMP_DEL
[3]
CLKDIV
PH[1]
FINE_DEL_
PRE[1]
SYNCO_
DEL[1]
N/A
PD
LST_EN
RCVLST
_IRQ
FSC[1]
FSC[9]
[1]
LVDS0_HI
DCI_DEL[5]
DCI_DEL[3]
Bit 0
N/A
DAC_BIAS
_PD
MU_CNT_
CLK
RCV_
LCK_EN
RCVLCK
_IRQ
N/A
FSC[0]
FSC[8]
DAC_DEC
[0]
N/A
LVDS_
Bias[0]
HNDOFF_
Rise[0]
DCI_PST
_PH0
LVDS0_LO
N/A
N/A
RCVR_
CNT_ENA
RCVR_
GAIN[0]
SMP_DEL
[2]
FINE_DEL_
SKW[0]
DCI_DEL[4]
LCKTHR[0]
SYNCO_
DEL[0]
N/A
SYNCSH_
DEL[1]
SMP_FINE_
DEL[0]
SMP_DEL
[2]
CLKDIV
PH[0]
DCI_DEL[2]
FINE_DEL_
PRE[0]
SYNCO_
DEL[0]
AD9739
Default
0x00
0x00
0x03
0x00
0x00
N/A
0x00
0x02
0x00
N/A
0x00
RNDM
RNDM
RNDM/0
N/A
N/A
0x42
0xDD
0x29
0x71
0x0A
0x42
0x00
0x00
0x00
0xC7
0x29
0xC0
0x29
0x86
0x00