AD9739BBCZRL Analog Devices Inc, AD9739BBCZRL Datasheet - Page 41

• Manufacturer Part Number: AD9739BBCZRL
• Description: 14 Bit 2.5 GSPS DAC
• Manufacturer: Analog Devices Inc

Specifications of AD9739BBCZRL

• Number Of Bits: 14
• Data Interface: Serial
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 980mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 160-CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Settling Time: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

MU DELAY CONTROLLER
The mu delay controller adjusts timing between the digital and
analog blocks. The mu delay controller maintains phase
relational information between the digital and analog clock
domains. The control system continuously adjusts the mu delay
to maintain the desired phase relationship between the digital
and analog sections. A top level diagram of the mu delay
controller within the DAC is shown in Figure 88.
CLOCK
The mu delay controller has two modes of operation: initial
phase search and phase tracking. In the phase search mode,
the controller looks for the initial mu delay value to use before
going into tracking mode. In tracking mode, the controller
makes adjustments to the initial mu delay value to keep the
phase at the desired value. The initial phase search is required
because there may be multiple mu delay settings that give the
desired phase, but the device may not operate correctly at all of
the mu delay values.
MU CONTROL OPERATION
The mu delay controller is enabled via Register 0x26, Bit 0.
Before enabling the controller, it is important to turn on both
the phase comparator boost (Register 0x24, Bits[5:4]) and the
mu delay controller duty cycle correction circuitry (Register
0x25, Bit 7). Both of these functions allow for more robust
operation of the mu delay controller over the entire operating
speed of the part. There are three modes of operation for the
mu controller specified by the Mode[1:0], Bits[5:4] in Register
0x26, which are as follows:
•
•
•
Search Mode
The search algorithm begins at a specified mu delay value set
via MUDEL[8:0] (MUDEL [0], Bit 7 in Register 0x27 and
MUDEL[8:1], Bits[7:0] in Register 0x28). Even though there
are nine bits of resolution for this delay line value, the maximum
allowable mu delay is 432 (decimal). The optimal point to begin
the search is in the middle of the delay line, that is, at approx-
imately 216.
The initial search algorithm works by sweeping through
different mu delay values until the desired
which is specified by SetPhs, Bits[4:0] in Register 0x27, with the
maximum allowable phase being 16. When the desired phase is
DAC
Search and track (0x0) (optimal setting)
Track only (0x1)
Search only (0x2)
14-BIT DATA
Figure 88. Mu Delay Controller Block Diagram
DELAY
MU
CIRCUITRY
DIGITAL
CONTROLLER
DELAY
MU
14-BIT DATA
DETECTOR
PHASE
phase is measured,
CIRCUITRY
ANALOG
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IP
IN
measured, the slope of the phase measurement is calculated and
compared against the desired slope, which is specified by the
Slope bit in Register 0x26. A positive slope occurs when the
measured phase increases as the mu delay increases. A negative
slope occurs when the phase decreases as the mu delay increases.
For optimal ac performance, the desired setting for the search is
a negative slope and a phase value of 6. If everything matches,
the search algorithm is finished. The Search_Tol bit (Register
0x29, Bit 7) can
as follows:
•
•
Figure 89 shows a typical plot of the mu phase vs. the mu delay
line value at 2.4 GSPS. Starting at the selected mu delay value,
the search direction can be specified via SrchMode[1:0],
Bits[6:5] found in Register 0x27. There are three possible
choices for the search.
•
•
•
If the mode is alternating, the search proceeds in both directions
until a programmable guard band is reached in one of the
directions, as specified by Guard[4:0], Bits[4:0] in Register
0x29. When the guard band is reached, the search continues,
only in the opposite direction. If the desired phase is not found
before the guard band is reached in the second direction, then
the search changes back to the alternating mode and continues
looking in the guard band. The search fails if the mu delay con-
troller reaches the endpoints. If the controller does not find the
desired phase during the search, ContRst, Bit 5 in Register 0x29
determines the corrective action as follows:
•
•
Not exact (0x0)—can find a phase within two values of the
desired phase
Exact (0x1)—finds the exact phase specified (optimal setting)
Down only (0x0)
Up only (0x1)
Alternating up and down (0x2) (optimal setting)
Continue (0x0)—continues to search (optimal setting)
Reset (0x1)
18
16
14
12
10
Figure 89. Typical Mu Phase Characteristic Plot @ 2.4 GSPS
8
6
4
2
0
0
GUARD
DESIRED
PHASE
BAND
40
be used to specify the accuracy of the search
80
SEARCH STARTING
120
LOCATION
160
MU DELAY
200
240
280
320
360
GUARD
BAND
400
AD9739
440