ADAV803ASTZ-REEL Analog Devices Inc, ADAV803ASTZ-REEL Datasheet - Page 16

• Manufacturer Part Number: ADAV803ASTZ-REEL
• Description: IC,Soundcard Circuits,QFP,64PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Type: Audio Codecr

Specifications of ADAV803ASTZ-REEL

• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: No
• Dynamic Range, Adcs / Dacs (db) Typ: 102 / 101
• Voltage - Supply, Analog: 3 V ~ 3.6 V
• Voltage - Supply, Digital: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADAV803EBZ - BOARD EVALUATION FOR ADAV803
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADAV803
Automatic Level Control (ALC)
The ADC record channel features a programmable automatic
level control block. This block monitors the level of the ADC
output signal and automatically reduces the gain, if the signal at
the input pins causes the ADC output to exceed a preset limit.
This function can be useful to maximize the signal dynamic
range when the input level is not well defined. The PGA can be
used to amplify the unknown signal, and the ALC reduces the
gain until the ADC output is within the preset limits. This
results in maximum front end gain.
Because the ALC block monitors the output of the ADC, the
volume control function should not be used. The ADC volume
control scales the results from the ADC, and any distortion
caused by the input signal exceeding the input range of the
ADC is still present at the output of the ADC, but scaled by a
value determined by the volume control register.
The ALC block has two functions, attack mode and recovery
mode. Recovery mode consists of three settings: no recovery,
normal recovery, and limited recovery. These modes are
discussed in the following sections. Figure 26 is a flow diagram
of the ALC block. When the ALC has been enabled, any
changes made to the PGA or ALC settings are ignored. To
change the functionality of the ALC, it must first be disabled.
The settings can then be changed and the ALC re-enabled.
Attack Mode
When the absolute value of the ADC output exceeds the level
set by the attack threshold bits in ALC Control Register 2, attack
mode is initiated. The PGA gain for both channels is reduced by
one step (0.5 dB). The ALC then waits for a time determined by
the attack timer bits before sampling the ADC output value
again. If the ADC output is still above the threshold, the PGA
gain is reduced by a further step. This procedure continues until
the ADC output is below the limit set by the attack threshold
bits. The initial gains of the PGAs are defined by the ADC left
PGA gain register and the ADC right PGA gain register, and
they can have different values. The ALC subtracts a common
gain offset to these values. The ALC preserves any gain
difference in dB as defined by these registers. At no time do the
PGA gains exceed their initial values. The initial gain setting,
therefore, also serves as a maximum value.
The limit detection mode bit in ALC Control Register 1
determines how the ALC responds to an ADC output that
exceeds the set limits. If this bit is a 1, both channels must
exceed the threshold before the gain is reduced. This mode can
be used to prevent unnecessary gain reduction due to spurious
noise on a single channel. If the limit detection mode bit is a 0,
the gain is reduced when either channel exceeds the threshold.
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No Recovery Mode
By default, there is no gain recovery. Once the gain has been
reduced, it is not recovered until the ALC is reset, either by
toggling the ALCEN bit in ALC Control Register 1 or by
writing any value to ALC Control Register 3. The latter option
is more efficient because it requires only one write operation to
reset the ALC function. No recovery mode prevents volume
modulation of the signal caused by adjusting the gain, which
can create undesirable artifacts in the signal. The gain can be
reduced but not recovered. Therefore, care should be taken that
spurious signals do not interfere with the input signal because
these might trigger a gain reduction unnecessarily.
Normal Recovery Mode
Normal recovery mode allows for the PGA gain to be recovered,
provided that the input signal meets certain criteria. First, the
ALC must not be in attack mode, that is, the PGA gain has been
reduced sufficiently such that the input signal is below the level
set by the attack threshold bits. Second, the output result from
the ADC must be below the level set by the recovery threshold
bits in the ALC control register. If both of these criteria are met,
the gain is recovered by one step (0.5 dB). The gain is
incrementally restored to its original value, assuming that the
ADC output level is below the recovery threshold at intervals
determined by the recovery time bits.
If the ADC output level exceeds the recovery threshold while
the PGA gain is being restored, the PGA gain value is held and
does not continue restoration until the ADC output level is
again below the recovery threshold. Once the PGA gain is
restored to its original value, it is not changed again unless the
ADC output value exceeds the attack threshold and the ALC
then enters attack mode. Care should be taken when using this
mode to choose values for the attack and recovery thresholds
that prevent excessive volume modulation caused by continuous
gain adjustments.
Limited Recovery Mode
Limited recovery mode offers a compromise between no recov-
ery and normal recovery modes. If the output level of the ADC
exceeds the attack threshold, attack mode is initiated. When
attack mode has reduced the PGA gain to suitable levels, the
ALC attempts to recover the gain to its original level. If the
ADC output level exceeds the level set by the recovery threshold
bits, a counter is incremented (GAINCNTR). This counter is
incremented at intervals equal to the recovery time selection, if
the ADC has any excursion above the recovery threshold. If the
counter reaches its maximum value, determined by the
GAINCNTR bits in ALC Control Register 1, the PGA gain is
deemed suitable and no further gain recovery is attempted.
Whenever the ADC output level exceeds the attack threshold,
attack mode is reinitiated and the counter is reset.