ADAV803 Analog Devices, ADAV803 Datasheet
ADAV803
Available stocks
Related parts for ADAV803
ADAV803 Summary of contents
Page 1
... ADAV803 is controlled via an I C-compatible serial interface, which allows the programming of individual control register settings. The ADAV803 operates from a single analog 3.3 V power supply and a digital power supply of 3.3 V with optional digital interface range of 3 3.6 V. The part is housed in a 64-lead LQFP package and is character- ized for operation over the commercial temperature range of − ...
Page 2
... ADAV803 TABLE OF CONTENTS Specifications..................................................................................... 3 Test Conditions............................................................................. 3 ADAV803 Specifications ............................................................. 3 Timing Specifications .................................................................. 6 Temperature Range ...................................................................... 7 Absolute Maximum Ratings............................................................ 8 ESD Caution.................................................................................. 8 Pin Configuration and Function Descriptions............................. 9 Typical Performance Characteristics ........................................... 11 Functional Description .................................................................. 15 ADC Section ............................................................................... 15 DAC Section................................................................................ 18 Sample Rate Converter (SRC) Functional Overview ............ 19 PLL Section ................................................................................. 22 REVISION HISTORY 7/04— ...
Page 3
... Ambient Temperature Master Clock (XIN) Measurement Bandwidth Word Width (All Converters) Load Capacitance on Digital Outputs ADC Input Frequency DAC Output Frequency Digital Input Digital Output ADAV803 SPECIFICATIONS Table 2. Parameter PGA SECTION Input Impedance Minimum Gain Maximum Gain Gain Step REFERENCE SECTION ...
Page 4
... ADAV803 Parameter Maximum Volume Attenuation Mute Attenuation Group Delay kHz kHz S ADC LOW-PASS DIGITAL DECIMATION FILTER CHARACTERISTICS Pass-Band Frequency Stop-Band Frequency Stop-Band Attenuation Pass-Band Ripple ADC HIGH-PASS DIGITAL FILTER CHARACTERISTICS Cutoff Frequency SRC SECTION Resolution Sample Rate SRC MCLK ...
Page 5
... Rev Page ADAV803 Comments Sample rate: 44.1 kHz Sample rate: 48 kHz Sample rate: 96 kHz Sample rate: 44.1 kHz Sample rate: 48 kHz Sample rate: 96 kHz Sample rate: 44.1 kHz Sample rate: 48 kHz Sample rate: 96 kHz Sample rate: 44.1 kHz Sample rate: 48 kHz Sample rate: 96 kHz 256/384/512/768 × ...
Page 6
... ADAV803 Parameter Power-Down Current Analog Current Digital Current Digital Interface Current DIRIN/DIROUT Current PLL Current Power Supply Rejection Signal at Analog Supply Pins 1 Guaranteed by design. TIMING SPECIFICATIONS Timing specifications are guaranteed over the full temperature and supply range. Table 3. Parameter MASTER CLOCK AND RESET ...
Page 7
... Functionality Guaranteed Storage Min Typ Max Unit Min Typ Max Unit 25 °C −40 +85 °C −65 +150 °C Rev Page ADAV803 Comments From xBCLK falling edge From xBCLK falling edge From xBCLK rising edge From xBCLK rising edge ...
Page 8
... ADAV803 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Rating DVDD to DGND and ODVDD 4.6 V DGND AVDD to AGND 4.6 V Digital Inputs DGND − 0 DVDD + 0.3 V Analog Inputs AGND − 0 AVDD + 0.3 V AGND to DGND −0 +0.3 V Reference Voltage Indefinite short circuit to ground Soldering (10 s) 300° ...
Page 9
... DVDD 16 DGND Figure 2. Pin Configuration 2 C-Compatible Control Interface Compatible Control Interface. Rev Page ADVDD 47 ADGND 46 PLL_LF2 45 PLL_LF1 44 PLL_GND 43 PLL_VDD 42 DGND 41 SYSCLK1 40 SYSCLK2 39 SYSCLK3 38 XIN 37 XOUT 36 MCLKO 35 MCLKI 34 DVDD 33 DGND ADAV803 ...
Page 10
... ADAV803 Pin No. Mnemonic I/O Description 27 OAUXLRCLK I/O Sampling Clock (LRCLK) of Auxiliary Digital Output Port. 28 OAUXBCLK I/O Serial Clock (BCLK) of Auxiliary Digital Output Port. 29 OAUXSDATA O Data Output of Auxiliary Digital Output Port. 30 IAUXLRCLK I/O Sampling Clock (LRCLK) of Auxiliary Digital Input Port. 31 IAUXBCLK I/O Serial (BCLK) of Auxiliary Digital Input Port. ...
Page 11
... S 0.06 0.04 0.02 0.00 –0.02 –0.04 –0. kHz S Rev Page ADAV803 96 192 288 FREQUENCY (kHz) Figure 6. DAC Composite Filter Response, 48 kHz FREQUENCY (kHz) Figure 7. DAC Pass-Band Filter Response, 48 kHz 8 16 FREQUENCY (kHz) Figure 8. DAC Filter Ripple, 48 kHz 384 48 24 ...
Page 12
... ADAV803 0 –50 –100 –150 0 192 384 FREQUENCY (kHz) Figure 9. DAC Composite Filter Response, 96 kHz 0 –50 –100 –150 FREQUENCY (kHz) Figure 10. DAC Pass-Band Filter Response, 96 kHz 0.10 0.05 0.00 –0.05 –0. FREQUENCY (kHz) Figure 11. DAC Filter Ripple, 96 kHz 0 –50 –100 –150 –200 576 ...
Page 13
... Rev Page ADAV803 THD+N = 95dB FREQUENCY (kHz) Figure 18. DAC THD + kHz S DNR = 102dB (A-Weighted FREQUENCY (kHz) Figure 19. ADC Dynamic Range, f ...
Page 14
... ADAV803 0 –20 –40 –60 –80 –100 –120 –140 –160 FREQUENCY (kHz) Figure 21. ADC Dynamic Range, f DNR = 102dB (A-Weighted) –100 –120 –140 –160 kHz S Rev Page D+N = 92dB – –3dB) IN –40 –60 – FREQUENCY (kHz) Figure 22 ...
Page 15
... FUNCTIONAL DESCRIP TION ADC SECTION The ADAV803’s ADC section is implemented using a second- order multibit (5 bits) Σ-∆ modulator. The modulator is sampled at either half of the ADC MCLK rate (modulator clo = 128 × one-quarter of the ADC MCLK rate (modulator S clock = 64 × ...
Page 16
... ADAV803 Automatic Level Control ( ALC) The ADC record channel features a programmable automatic level control block. This block monitors the level of the ADC output signal and automatically reduces the gain, if the signal the input pins causes the ADC output to exceed a preset limi This function can be useful to maximize the signal dynamic range when the input level is not well defined ...
Page 17
... For best performance of the ADC, avoid using similar fre- quency clocks from separate sources in the ADAV803. For example, running the ADC from a 12.288 MHz clock connected to MCLKI and using the PLL to generate a separate 12.288 MHz ...
Page 18
... Note that the DACs are muted by def prevent unwanted pops, clicks, and other noises from appearing on the outputs while the ADAV803 is being configured. Each DAC also has a peak-level register that records the peak value of the digital audio data. Reading the register clears the peak. ...
Page 19
... The error can be S_OUT significantly reduced, however, through interpolation of t input data Therefore, the sample rate converter in t S_IN ADAV803 is concep tually interpolated by a factor of 2 ZERO-ORDER IN HOLD f =1/T1 S_IN ORIGINAL SIGNAL ...
Page 20
... ADAV803 The worst-case images can be computed from the zero-order hold frequency response: maximum image = sin (× F/f S_INTERP where the frequency of the worst-case image that would × f ± f /2. S_IN S_IN × S_INTERP S_IN The following worst-case image ...
Page 21
... The ratio is S_IN S_OUT S_OUT counter > the ratio is held at one. S_IN S_OUT S_IN , the sample rate ratio is updated different S_OUT periods from the previous f S_OUT ADAV803 the digital p register de > S_IN 20 ) × 2 ratio for 10k 100k is the X-Axis, S_IN ...
Page 22
... PLL1 and PLL2, are selected. y The clock nodes, PLL1 and PLL2, can be used as master c for the other blocks in the ADAV803 such as the DAC or ADC. The PLL has separate supply and ground pins, which sh ratios. as clean as possible to prevent electrical noise from being ...
Page 23
... VCO of the clock recovery PLL. The recovered audio data and audio clock can be routed to the different blocks of the ADAV803, as required. Figure 39 shows a conceptual diagram of the DIRIN block. PLL1 MCLK ...
Page 24
... The user bits accumulate over 1,176 frames when the interconnect is imple- menting the so-called subcode scheme organization of the channel status block, frames, and subframe is shown in Table 9 and Table 10. Note that the ADAV803 supports the profess point of view only. The digital interface supports only c onsumer mode ...
Page 25
... Receiver Section The ADAV803 uses a double-buffering scheme to handle read- ing channel status and user bit information. The channel status bits are available as a memory buffer, taking up 24 consecutive register locations ...
Page 26
... ADAV803 Table 11. RxBCONF3 Functionality RxBCONF0 Receiver Us er Bit Buffer Size 0 384 bits with Preamble Z as the start of the block. 1 768 bits with Preamble Z as the start of the block. The updating of the user bit buffer is controlled by Bits RxBCONF2–1 and Bit 7 to Bit 4 of the channel status register, as shown in Table 12 and Table 13. Table 12. RxBCONF2– ...
Page 27
... INTRPT 0 1 SERIAL DATA PORTS The ADAV803 contains four flexible serial ports (SPORTs) to allow data transfer to and from the codec. All four SPORTs are independent and can be configured as master or slave ports. In slave mode, the xLRCLK and xBCLK signals are inputs to the serial ports ...
Page 28
... Figure timing diagram of BITS 4-3 the serial data port formats. SRC Clocking Scheme MCLK The ADAV803 provides a f DIVIDER chip clocking sources. The on-c REG 0x00 intended to offer complete system clocking requirements for BITS 1-0 use with available MPEG encoders, decoders combination of codecs ...
Page 29
... S/PDIF port (single-wire from the on-chip transmitter). Internally, the DIR and DIT are interfaced via 3-wire interfa The datapath for each input and output port is selected by programming Datapath Control Registers 1 and 2. Figure 52 shows the internal datapath structure of the ADAV803. PLL ADC clude the REFERENCE ces ...
Page 30
... ADAV803. Finally the user can send another frame with the eight data bits required to be written to the register. A third ACK is issued by the ADAV803, after which the user can send a stop condition to complete the data transfer. A read operation requires that the user first write to the ADAV803 to point to the correct register and then read the data ...
Page 31
... REPEATE D START BY MA STER BLOCK REA WRITES The ADAV803 provid es the user with th r ead from a block of re gisters in one contin us e this feature, the us er has to continue b efore the stop conditi on. For a write opera address is auto maticall ...
Page 32
... ADAV803 REGISTER DESCRIPTIONS Table 17. SRC and Cl ock Control Register SRCDIV 1 SRCDIV0 7 6 ADDRESS = 0000000 (0x00) SRCDIV1–0 Divides the SRC master clock SRC master clock is not divided SRC master clock 10 = SRC master clock is divided by 2. 11= SRC master cloc CLK2DIV1–0 Clock divid er for Internal Clock 2 (ICLK2) ...
Page 33
... SPMODE1–0 Selects the serial format of the 00 = Left-justified Reserved Right-justified. RES CLKSRC1 port. ustified. CLKSRC1 CLKSRC0 5 4 erating the OL RCLK and OBCLK. record port. Rev Page CLKSRC0 SPMODE 2 SPMODE1 WLEN1 WLEN0 SPMODE1 ADAV803 SPMODE0 0 SPMODE0 0 ...
Page 34
... ADAV803 Table 22. Auxiliary Output Port Register RES RES 7 6 ADDRESS = 0000111 (0x07) CLKSRC1–0 Selects the clock source for generating the OAUXLRCLK and OAUXB 00 = Auxiliary record port is a slave Recovered PLL clock Internal Clock Internal Clock 2. WLEN1–0 Selects the serial output word length. ...
Page 35
... PLL. reference clock to the PLL when SP_PLL is set. the SRC. s not allowed into the SRC, if the NONAUDIO bit is set. the AES3/SPDIF receiver is not allowed into the SRC. Rev Page ADAV803 ERR1–0 LOCK1– RES ...
Page 36
... ADAV803 Table 26. Receiver Buffer Configuration Register RES 7 ADDRESS = 0001011 (0x0B) RxBCONF5 If the user bits are formatted according to the IEC60958-3 standard and the DAT category is detected, the user bit interrupt is enabled only when there is a change in the start (ID) bit User bit interrupt is enabled in normal mode. ...
Page 37
... Channel Status B buffer. tus is disabled. channel status buffer. itter Channel Status A buffer can be accessed at address locations 0x38 through 0x4F Significant Byte Rev Page TxBCONF2–1 TxBCONF0 RES RES TxCSSWITCH nsmitter channel status buffer to the SPDIF transmitter ADAV803 RxCSSWITCH 0 ...
Page 38
... ADAV803 Table 31. Transmitter Message Zeros Least Signif LSBZeros7– ADDRESS = 0010000 (0x10) LSBZeros7–0 Least significant byte of the number of zeros to be stuffed between IEC60958-3 messages (packets). Default = 0x09. T able 32. Autobuffer Register RES 7 ADDRESS = 0010001 (0x11) Zero_Stuff_IU Enables the addition or subtraction of zeros between IUs during autobuffering of the user bits in IEC60958-3 format. ...
Page 39
... Rev Page nonaudio data is detected according to the IEC60937 becomes the eight most significant bits CRCError NoStream BiPhase/ Parity naudio data c nges. ha ion of a pream ble . The nonau dio preamble type register ADAV803 Lock 0 ster ...
Page 40
... ADAV803 Table 40. Receiver Error Mask Register RxValid ity Mask 7 ADDRESS = 0011001 (0x19) RxValidity Mask Masks the RxValidity bit from gene 0 = RxValidity bit does not generate an interrupt RxValidity bit generates an interrupt. Masks the emphasis bit from generating an in Emphasis Mask 0 = Emphasis bit does not generate an interrupt. ...
Page 41
... Rev Page OVRR Ma sk MUT IND MASK 1 0 RxCSDIFF RxUBINT RxCSBINT ceiver Channel Status B clock. This bit the channel status ha changed ADAV803 E_ RxERROR 0 s when ...
Page 42
... ADAV803 Table 44. Interrupt Status Mask Register SRCError T xCSTINT Mask ADDRESS = 0011101 (0x1D) SRCError Mask Masks the SRCError bit from generating an interrupt SRCError bit does not generate an interrupt SRCError bit generates TxCSTINT Mas k Masks the TxCST 0 = TxCSTINT bit TxCSTINT bit generates a ...
Page 43
... Data Register DATA00 RES RES 5 4 Rev Page dress loca tion 0 x20, Bit 0. This bu ceiver an d trans mitter. tored a t address location 0x38, Bit 0. This buffer is enabled. iver use r bit bu ffer. RES RES QCRCERROR ADAV803 ffer is rea d QSUB 0 ...
Page 44
... ADAV803 Table 54. Q Subcode Buffer Addres s Bit 0x55 Address Address 0x56 Track Tra ck number number 0x57 Index Index 0x58 Minute Minu te 0x59 Second Second 0x5A Frame Frame 0x5B Zero Zero 0x5C Absolute Absolute minute minute 0x5D Absolute Absolu te second ...
Page 45
... Left nega tive Right ne gative Both negative. MUTER Mute rig ht channel Normal Mute. MUTEL Mute left channel Normal Mute. DAC2 DAC1 5 4 IT. CHSEL1 CHSEL0 5 4 wer-down . level. REF Rev Page DAC0 DIT2 DIT1 POL1 POL0 MUTER ADAV803 DIT0 0 MUTEL 0 ...
Page 46
... ADAV803 Table 58. DAC Control Register 2 RES RES 7 6 ADDRESS = 1100101 (0x65) DMCLK1–0 DAC MCLK divider MCLK MCLK/1. MCLK/ MCLK/3. DFS1–0 DAC interpolator × (M CLK = 256 × × (MCLK 128 × × (MCLK = 64 × Reserved. DAC de-emphasis s D EEM1– ...
Page 47
... DLP5 DLP4 DRP5 DRP4 5 4 ter AGL5 AGL4 5 4 Rev Page DVOLL 3 DVOLL 2 DVOLL DVOLR3 DVOLR2 DVOLR1 DLP3 DLP2 DLP1 DRP3 DRP2 DRP1 AGL3 AGL2 AGL1 ADAV803 DVOLL 0 0 DVOLR0 0 DLP0 0 DRP0 0 AGL0 0 ...
Page 48
... ADAV803 Table 66. ADC Right Channel PGA Gain Register RES RES 7 6 ADDRESS = 1101101 (0x6D) AGR5–0 PGA right channel gain control. 000000 = 0 dB. 000001 = 0.5 dB. … 101111 = 23.5 dB. 110000 = 24 dB. … 111111 = 24 dB. Table 67. ADC Control Register 1 AMC HPF 7 6 ADDRESS = 1101110 (0x6E) AMC ADC modulator clock ...
Page 49
... AVOLR5 AVOLR4 ntrol. BFS). ). ALP 5 ALP4 5 4 ARP5 ARP4 5 4 Rev Page RES RES MCD1 AVOLL3 AVOLL2 AVOLL1 AVOLR3 AVOLR2 AVOLR1 ALP3 ALP2 ALP1 ARP3 ARP2 ARP1 ADAV803 MCD0 0 AVOLL0 0 AVOLR0 0 ALP0 0 ARP0 0 ...
Page 50
... ADAV803 Table 73. PLL Control Register 1 DIRIN_C LK1 DIRIN_C 7 6 ADDRESS = 1110100 (0x74) DIRIN_CLK1-0 Recovered SPDIF clock SYSCLK3 comes from PLL block Reserved . 10 = Reserved SYSCLK3 is the recovered SPDIF clock from DIRIN. Divide input MCLK CLKODIV 0 = Disabled Enabled . Divide XIN generate the PLL master clock ...
Page 51
... PLL2 internal selector (see Figure 38 FS2 FS2/ FS3 FS3/2. PLL1INT PLL1 internal selector FS1 FS1/2. egister 1 CLK1 D LK0 C AC LK2 RES ICLK1_1 5 4 Rev Page ACLK1 ACLK0 I CLK2 ICLK1_0 PLL2INT1 PLL2INT0 ADAV803 ICLK2 _0 0 PLL1INT 0 ...
Page 52
... ADAV803 Table 77. PLL Clock Source Regist er PLL1_Sour ce 7 ADDRESS = 1111000 (0x78) PLL1_Source Selects the clock source for PLL1 XIN MCLKI. PLL2_Source Selects the clo ck source for PLL2 XIN MCLKI. Table 78. PLL Output Enable Register RES RES 7 6 ADDRESS = 1111010 (0x7A) This bit powers down the SPDIF receiver. ...
Page 53
... RECTIME1–0 Recovery time selection ms ms 128 ms 256 ms. ATKTIME Attack timer selection ms ms. GAINCNTR1–0 RECMODE1– RECTH1–0 ATKTH1– Rev Page ADAV803 LIMDET ALCEN 1 0 RECTIME1–0 ATKTIME ...
Page 54
... ADAV803 Table 81. ALC Control Register 3 ALC RESET ADDRESS = 1111101 (0x7D) ALC RESET A write to this register restarts the ALC operation. The value written to this register is irrelevant. A read from this register gives the gain reduction factor. Rev Page ...
Page 55
... XIN and XOUT pins is still active, so that a stable clock source is available when the ADAV803 is taken out of reset. Also, the VCO associated with the SPDIF receiver is active so that the receiver locks to the incoming SPDIF stream in the shortest possible time ...
Page 56
... Range ADAV803ASTZ 1 −40°C to +85° ADAV803ASTZ-REEL −40°C to +85° free part Purchase of licensed I²C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I²C Patent Rights to use these components in an I²C system, provided that the system conforms to the I²C Standard Specification as defined by Philips. ...