ADAV803 Analog Devices, ADAV803 Datasheet - Page 50

• Manufacturer Part Number: ADAV803
• Description: Audio Codec
• Manufacturer: Analog Devices

ADAV803
Table 73. PLL Control Register 1
ADDRESS = 1110100 (0x74)
DIRIN_CLK1-0
M
PLLDIV
PLL2PD
PLL1PD
XTLPD
SYSCLK3
Table 74. PLL Control Register 2
ADDRESS = 1110101 (0x75)
FS2_1–0
SEL2
DO
FS1–0
SEL1
DOUB1
CLKODIV
UB2
DIRIN_C
7
Recovered SPDIF clock se
00 = SYSCLK3 comes from PLL block.
01 = Reserved
10 = Reserved.
11 = SYSCLK3 is
Divide input MCLK by 2 to
0 = Disabled.
1 = Enabled
Divide XIN b
0 = Disabled.
1 = Enabled
Power-down P
0 = Normal.
1 = Power-down.
Power-down PLL1.
0 = Normal.
1 = Power-d
Power-dow
0 = Normal.
1 = Power-
Clock output
0 = 512 × f
1 = 256 × f
FS2_1
7
Sampl rate se
00 = 48 kHz.
01 = Reserved.
10 = 32 kH
11 = 44.1 kHz
Oversample rat
0 = 256 × f
1 = 384 × f
Double-se
0 = Disabled.
1 = Enable
Sample rate
00 = 48 kHz.
01 = Rese
10 = 32 kHz
11 = 44.1 kHz.
Oversample ratio select for PLL1.
0 = 256 × f
1 = 384 × f
Double-selected sample rate on PLL1.
0 = Disabled.
1 = Enabled.
e
LK1
rved.
S
S
lected sample rate on PLL2.
down.
S
S
d.
S
S
z.
.
.
n XTAL oscillator.
.
.
.
.
.
.
.
own.
y 2 to generate the PLL master clock.
select for PLL1.
for SYSCLK3.
.
.
LL2.
lec
FS2_0
6
io select for PLL2.
DIRIN_C
6
the recovered SPDIF clock from DIRIN.
t for PLL2.
LK0
nt to SYSCLK3.
generate MCLKO.
SEL2
5
MCLKO
5
Rev. 0 | Page 50 of 56
DIV
DOUB2
4
PLLDIV
4
FS1
3
PLL2PD
3
FS0
2
PLL1PD
2
SEL1
1
XTLPD
1
DOUB1
0
SYSCLK3
0