ADAV803 Analog Devices, ADAV803 Datasheet - Page 15

• Manufacturer Part Number: ADAV803
• Description: Audio Codec
• Manufacturer: Analog Devices

FUNCTIONAL DESCRIP
ADC SECTION
The ADAV803’s ADC section is implemented using a second-
order multibit (5 bits) Σ-∆ modulator. The modulator is
sampled at either half of the ADC MCLK rate (modulator clo
= 128 × f
clock = 64 × f
followed by a cascade of three half-band FIR filters. The Sin
decimates by a factor of 16 at 48 kHz
96 kHz. Each of the half-band filters decimates by a factor of 2.
Figure 23 shows the details of the ADC section. The ADC can
be clocked by a number of different clock sources to control t
sample rate. MCLK selection for the ADC is set by Internal
Clocking Control Register 1 (Address 0x76). The ADC provide
an output word of up to 24 bits of resolution in twos comple-
ment format. The output word can be routed to ei
output ports, the sample rate converter, or the SPDIF digital
transmitter.
S
) or one-quarter of the ADC MCLK rate (modulator
S
). The digital decimator consists of a Sinc^5 filter
Figure 23. Clock Path Control on the ADC
ADC MODCLK
ADC MCLK
DIVIDER
MCLK
ADC
ADC
MODULATOR
MULTI-BIT
(TYP 6.144MHz)
ADC MCLK/2
Σ–∆
REG 0x6F
BITS 1–0
TION
REG 0x76
BITS 4–2
and by a factor of 8 at
DECIMATOR
SINC^5
ther the
384kHz
768kHz
Figure 25 . ADC Block
HALF-BAND
c
CONTROL
Rev. 0 | Page 15 of 56
VOLUME
FILTER
ck
he
s
192k
384k
Hz
Hz
Programmable Gain Amplifier (PGA)
The input of the record channel features a PGA that converts
the single-ended signal to a differential signal, which is applied
to the analog Σ-Δ modulator of the ADC. The PGA can be
programmed to amplify a signal by up to 24 dB in 0.5 dB
increments. Figure 24 shows the structure of the PGA circuit.
Analog Σ-∆ Modulator
The ADC features a second-order, multibit, Σ-Δ modulator. The
input features two integrators in cascade followed by a flash
converter. This multibit output is directed to a scrambler,
followed by a DAC for loop feedback. The flash ADC output is
also converted from thermometer coding to binary coding for
input as a 5-bit word to the decimator. F igure 25 shows the
ADC block diagram.
The ADC also features independent digital volume control for
the left and right channels. The volume control consists of
256 linear steps, with each step reducing the digital output
codes by 0.39%. Each channel also has a peak detector that
records the peak level of the input signal. The peak detector
register is cleared by reading it.
Diagram
VREF
HPF
COMPENSATION
4kΩ
8kΩ
SINC
4kΩ TO 64kΩ
8kΩ
DETECT
192kHz
PEAK
96kHz
Figure 24. PGA Block Diagram
CAPACITOR
CAPACITOR
EXTERNAL
EXTERNAL
(1nF NPO)
125Ω
125Ω
(1nF NPO)
HALF-BAND
FILTER
CAPxN
CAPxP
CAPACITOR
EXTERNAL
48kHz
96kHz
(1nF NPO)
MODULATOR
ADAV803
TO