ADAV803 Analog Devices, ADAV803 Datasheet - Page 52

• Manufacturer Part Number: ADAV803
• Description: Audio Codec
• Manufacturer: Analog Devices

ADAV803
Table 77. PLL Clock Source Regist
ADDRESS = 1111000 (0x78)
PLL1_Source
PLL2_Source
Table 78. PLL Output
ADDRESS = 1111010 (0x7A)
DIRINPD
DIRIN_PIN
S
S
S
YSCLK1
YSCLK2
YSCLK3
PLL1_Sour
7
Selects the clock source for PLL1.
0 = XIN.
1 = MCLKI.
Selects the clo
0 = XIN.
1 = MCLKI.
RES
7
This bit powers down the SPDIF receiver.
0 = Normal.
1 = Power-down.
This bit determines the input levels of the DIRIN pin.
0 = DIRIN accepts input signals
1 = DIRIN accepts input signals as defined in the Specificati
Enables the SYSCLK1 output.
0 = Enabled.
1 = Disabled.
Enables the SYSC
0 = Enabled.
1 = Disabled.
Enabl
0 =
1 = Disa
Enable
Enabled.
es the SYSCLK3 ou
bled.
Register
ce
er
ck source for PLL2.
RES
6
PLL2_Source
6
LK2 output.
tput.
DIRINPD
5
down to 200 mV according to AES3 requirements.
RES
5
Rev. 0 | Page 52 of 56
DIRIN_PIN
4
RES
4
ons section.
RES
3
R
3
ES
SYSCLK1
2
RES
2
SYSCLK2
1
RES
1
SYSCLK3
0
RES
0