ADAV803 Analog Devices, ADAV803 Datasheet - Page 21

• Manufacturer Part Number: ADAV803
• Description: Audio Codec
• Manufacturer: Analog Devices

The number of inp
FIFO on the SRC is 16 plus Bit 6 to Bit 0 of the group delay
register. This feature is useful in varispeed applications to
prevent the read pointer to the FIFO from running ahead of the
write pointer. When set, Bit 7 of the group delay and mute-in
register soft-mutes the sample rate. Increasing the offset of the
write address pointer is useful for applications in which small
changes in the sample rate ratio between f
expected. The maximum decimation rate can be calculated
from the RAM word depth and the group delay as
for short group delay and
for long group delay.
The digital servo loop is essentially a ramp filter that provides
the initial pointer to the address in RAM and ROM for the start
of the FIR convolution. The RAM pointer is th
of the ramp filter, and the ROM is the fractional part. The
digital servo loop must provide excellent rejection of jitter on
the f
f
the fractional part of the ramp o
to dynamically alter the ROM coefficients wh
The digital servo loop is implemented with a multirate filter. To
settle the digital servo loop filter more quickly upon startup or a
change in the sample rate, a fast mode has been added to the
filter. When the digital servo loop starts up or the sample rate is
changed, the digital servo loop enters fast mode to adjust and
settle on the new sample rate. Upon sensing that the digital
S_OUT
S_IN
(512 − 16)/64 taps = 7.75
(512 − 64)/64 taps = 7
clock within 4.97 ps. The digital servo loop also divides
REG 0x76
and f
BIT 1
Figure 33. Clock and Datapath Control on the SCR
S_OUT
clocks, as well as measure the arrival of th
OUTPUT
ut samples added to the write pointer of the
MCLK
SRC
SRC
SRC
INPUT
SRC
REG 0x76
BIT 0
REG 0x00
BITS 1–0
utput by the ratio of f
REG 0x62
BITS 7–6
S_IN
ADC
AUXILIARY IN
PLAYBACK
DIR
and f
en f
e integer output
S_IN
S_OUT
> f
S_IN
are
S_OUT
/f
S_OUT
e
.
Rev. 0 | Page 21 of 56
s
serv loop returns to n
Dur g fast mode, the MUT _OUT b
r
be present in the digital audio data. The output of the SRC can
be muted by asserting Bit 7 of the group delay and mute
until the SRC has changed to slow mode. The MUTE_OUT bit
can be set to generate an interrupt when the SRC changes to
slow mode, indicating that the data is being sample rate
converted accurately.
The frequency responses of the digital servo loop for fast mo
and slow mode are shown in Figure 34. The FIR filter is a 64-tap
filter when f
f
starting address of the RAM address pointer and the ROM
address pointer from the digital servo loop at the start of the
f
decrementing its address by 1 for each tap, and the ROM
pointer increments its address by the (f
f
over, the convolution is completed.
The convolution is performed for both the left and right
channels, and the multiply accumulate circuit used for the
convolution is shared between the channels. The f
sample rate ratio circuit is used to dynamically alter the
coefficients in the ROM when f
calculated by comparing the output of an f
output of an f
If f
by more than two f
comparison. This is done to provide some hysteresis to prevent
the filter length from oscillating and causing distortion.
S_OUT
S_OUT
S_IN
ervo
egiste
Figure 34. Frequency Response of the Digital Servo Loop. f
S_IN
o
in
> f
–100
–120
–140
–160
–180
–200
–220
. The FIR filter performs its convolution by loading in the
–20
–40
–60
–80
period. The FIR filter then steps through the RAM by
loop is settling d
> f
r is asserted
S_OUT
0
0.01
S_OUT
or 2
S_OUT
, the sample rate ratio is updated, if it is different
S_IN
0.1
f
20
S_OUT
≥ f
counter. If f
for f
to let the u
S_OUT
S_IN
= 192 KHz, Master Clock is 30 MHz
1
S_OUT
SLOW MODE
own to reasonable value,
ormal
and is (f
periods from the previous f
FREQUENCY (Hz)
≥ f
E
10
S_OUT
(or slow) mo
ser know
a
S_IN
S_IN
S_IN
. Once the ROM address rolls
> f
100
/f
> f
S_OUT
S_IN
S_OUT
it in the sam le rate error
S_OUT
that clicks or pops might
, the ratio is held at one.
) ×
1k
. The ratio is
de.
S_OUT
FAST MODE
/f
64 taps when f
S_IN
counter to the
) × 2
10k
the digital
S_IN
S_IN
p
ADAV803
S_OUT
is the X-Axis,
20
/f
S_OUT
ratio for
100k
register
to f
S_IN
S_IN
de
>