ADAV803 Analog Devices, ADAV803 Datasheet - Page 41

• Manufacturer Part Number: ADAV803
• Description: Audio Codec
• Manufacturer: Analog Devices

Table 42. Sample Rate Converter Error Ma
ADDRESS = 0011011 (0x1B)
OVRL Mask
OVRR Mask
MUTE_IND M
Table 43. Interrupt St
ADDRESS = 0011100 (0x1C)
SRCError
TxCSTINT
TxUBINT
TxCSINT
RxCSDIFF
RxUBINT
RxCSBIN
RxERROR
T
ASK
RES
7
Masks the OVRL from generating an interrupt.
0 = OVRL bit does not generate an interrupt.
1 = OVRL bit generates an interrupt.
Masks the OVRR from generating an interrupt.
0 = OVRR bit does not generate an interrupt.
1 = OVRR bit generates an interrupt. Reserved.
Masks the MUTE_IND from generating an
0 = MUTE_IND bit does not generate an interrupt.
1 = MUTE_IND bit generates an interrupt.
atus Register
SRCError
7
This bit is set, if one of the sample rate converter interrupts is asserted, and the host should immediately read the
sample rate converter error register. This bit remains hi
This bit is set, if a write to the transmitter channel status buffer was made while transmitter channel status bits were
being copied from the transmitter CS buf
This bit is set, if the SPDIF transmit buffer is empty. T
This bit is set, if the transmitter channel status b
high until the interrupt status register is read.
This bit is set, if the receiver Channel Status A block is different from the re
remains high until read, but does not generate an interrupt.
This bit is set, if the rec
status register is read.
This b
Rx
This bit
receiver error register. This bit rema
BCONF3 = 1.
it is set, if
is set, if one of the AES3/SPDIF receiver interrupts is asserted, and the host should immediately read the
RES
6
TxCSTINT
6
a new
Th
is bit remains gh until the interrupt status register is read.
RES
5
block of c
sk Register
eiver user bit buffer has a new block or message. This bit remains high until the interrupt
TxUBINT
5
hannel sta
RES
4
hi
ins high until the interrupt status register is read.
Rev. 0 | Page 41 of 56
fer to the SPDIF transmit buffer.
interrupt.
tus is rea
RES
3
TxCSINT
4
it buffer has transmitted its block of channel status. This bit remains
d when RxBC NF3 =
his bit remains high until the interrupt status register is read.
OVRL Mask
2
gh until the interrupt status register is read.
RxCSDIFF
3
O
0, or if the
ceiver Channel Status B clock. This bit
RxUBINT
2
OVRR Ma
1
channel status ha changed
sk
RxCSBINT
1
MUT IND MASK
0
s
E_
ADAV803
RxERROR
0
when