ADAV803 Analog Devices, ADAV803 Datasheet - Page 32

• Manufacturer Part Number: ADAV803
• Description: Audio Codec
• Manufacturer: Analog Devices

ADAV803
REGISTER DESCRIPTIONS
Table
ADDRESS = 0000000 (0x00)
SRCDIV1–0
CLK2DIV1–0
CLK1DIV1–0
MCLKSEL1–0
Table 18. SPDIF Loop
ADDRESS = 0000011 (0x03)
TxMUX
Table 19. Playback Port Control Register
ADDRESS = 0000100 (0x04)
CLKSRC1–0
SPMODE2–0
17. SRC and Cl
ock
SRCDIV
7
Divides the SRC master clock.
00 = SRC master clock is not divided.
01 = SRC master clock
10 = SRC master clock is divided by 2.
11= SRC master cloc
Clock divid
00 = Divide by 1.
01 = Divide by 1.5.
10 = Divide by 2.
11 = Divide by 3.
Clock divider for Internal Clock 1 (ICLK1).
00 = Divide by 1.
01 = Divide by 1.5.
10 = D
11
Clock se
00 = Internal Clock 1.
01 = Internal Clock 2.
10 = PLL recovered clock (5
11 = PLL recovered clo
RES
7
Selects the source for SPDIF output (DITOUT).
0 = SPDIF transmitter, normal mode.
1 = DIRIN, loopback mode.
RES
7
Selects the clock source for generating the ILRCLK and IBCLK.
00 = Input port is a slave.
01 = Recovered PLL clock.
10 = Internal Clock 1.
11 = Internal Clock 2.
Selects the serial format of the playback port.
000 = Left-justified.
001 = I
100 = 24-bit, right-justified.
101 = 20-bit, right-justified.
110 = 18-bit, right-justified.
111 = 16-bit, right-justified.
back Control Register
= Divide by
Control Register
ivide by
2
S.
1
lection for the SRC master clock.
er for Internal Clock 2 (ICLK2).
SRCDIV0
6
2.
3.
RES
6
RES
6
k is divided by 3.
is divided by 1.5.
ck (256 × f
12 × f
CLK2DIV1
5
RES
5
RES
5
S
S
).
).
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CLK2DIV0
4
RES
4
CLKSRC1
4
CLK1DIV1
3
RES
3
CLKSRC0
3
CLK1DIV0
2
RES
2
SPMODE2
2
MCLKSEL1
1
RES
1
SPMODE1
1
MCLKSEL0
0
TxMUX
0
SPMODE0
0