ADCLK846/PCBZ Analog Devices Inc, ADCLK846/PCBZ Datasheet - Page 5

• Manufacturer Part Number: ADCLK846/PCBZ
• Description: Evaluation Kit 1.8V 6:VDS/12 CMOS Cl
• Manufacturer: Analog Devices Inc

Specifications of ADCLK846/PCBZ

• Design Resources: Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121)
• Main Purpose: Timing, Clock Buffer / Driver / Receiver / Translator
• Utilized Ic / Part: ADCLK846
• Primary Attributes: 6 LVDS/12 CMOS Outputs
• Secondary Attributes: CMOS, LVDS Outputs
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Embedded: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

CLOCK CHARACTERISTICS
Table 3. Clock Output Phase Noise
Parameter
CLK-TO-LVDS ABSOLUTE PHASE NOISE
CLK-TO-CMOS ABSOLUTE PHASE NOISE
LOGIC AND POWER CHARACTERISTICS
Table 4. Control Pin Characteristics
Parameter
CONTROL PINS
POWER
1
2
These pins each have a 200 kΩ internal pull-down resistor.
Change in T
1000 MHz
200 MHz
(CTRL_A, CTRL_B, SLEEP)
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Current
Logic 0 Current
Capacitance
Supply Voltage Requirement
LVDS Outputs, Full Operation
CMOS Outputs, Full Operation
Sleep
Power Supply Rejection
LVDS at 100 MHz
LVDS at 1200 MHz
CMOS at 100 MHz
CMOS at 250 MHz
LVDS
CMOS
PD
per change in V
2
1
S
.
Symbol
V
V
I
I
V
PSR
PSR
IH
IL
IH
IL
S
TPD
TPD
Min
V
5
−5
1.71
S
− 0.4
Min
Rev. B | Page 5 of 16
Typ
8
2
1.8
55
110
75
155
0.9
1.2
Typ
−90
−108
−117
−126
−134
−141
−146
−100
−117
−128
−138
−147
−153
−156
Max
0.4
20
+5
1.89
70
130
95
190
3
Unit
V
V
μA
μA
pF
V
mA
mA
mA
mA
mA
ps/mV
ps/mV
Max
Conditions
V
All outputs enabled as LVDS and loaded, R
All outputs enabled as LVDS and loaded, R
All outputs enabled as CMOS and loaded,
CMOS load = 10 pF
All outputs enabled as CMOS and loaded,
CMOS load = 10 pF
SLEEP pin pulled high; does not include power
dissipated in external resistors
S
= 1.8 V ± 5%
Unit
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Conditions
Input slew rate > 1 V/ns
At 10 Hz offset
At 100 Hz offset
At 1 kHz offset
At 10 kHz offset
At 100 kHz offset
At 1 MHz offset
At 10 MHz offset
Input slew rate > 1 V/ns
At 10 Hz offset
At 100 Hz offset
At 1 kHz offset
At 10 kHz offset
At 100 kHz offset
At 1 MHz offset
At 10 MHz offset
ADCLK846
L
L
= 100 Ω
= 100 Ω