ADF4117BRUZ-RL Analog Devices Inc, ADF4117BRUZ-RL Datasheet - Page 4
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ADF4117BRUZ-RL
Manufacturer Part Number
ADF4117BRUZ-RL
Description
IC,FREQUENCY SYNTHESIZER,BICMOS,TSSOP,16PIN,PLASTIC
Manufacturer
Analog Devices Inc
Type
Clock/Frequency Synthesizer (RF)r
Datasheet
1.ADF4116BRUZ-REEL.pdf
(28 pages)
Specifications of ADF4117BRUZ-RL
Pll
Yes
Input
CMOS
Output
Clock
Number Of Circuits
1
Ratio - Input:output
2:1
Differential - Input:output
Yes/No
Frequency - Max
1.2GHz
Divider/multiplier
Yes/No
Voltage - Supply
2.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
16-TSSOP
Frequency-max
1.2GHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ADF4117BRUZ-RL
Manufacturer:
ADI/亚德诺
Quantity:
20 000
ADF4116/ADF4117/ADF4118
Parameter
POWER SUPPLIES
NOISE CHARACTERISTICS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Operating temperature range for the B version is −40°C to +85°C.
Operating temperature range for the Y version is −40°C to +125°C.
This is the maximum operating frequency of the CMOS counters.
AC coupling ensures AV
Guaranteed by design.
T
The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO, PN
divider value) and 10logF
The phase noise is measured with the EVAL-ADF411xEB and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REF
(f
f
REFIN
f
f
f
f
f
A
REFOUT
REFIN
REFIN
REFIN
REFIN
REFIN
AV
DV
V
I
I
Low-Power Sleep Mode
ADF4118 Normalized Phase Noise
Phase Noise Performance
Spurious Signals
DD
P
= 25°C; AV
P
DD
ADF4116
ADF4117
ADF4118
Floor
ADF4116 540 MHz Output
ADF4117 900 MHz Output
ADF4118 900 MHz Output
ADF4117 836 MHz Output
ADF4118 1750 MHz Output
ADF4118 1750 MHz Output
ADF4118 1960 MHz Output
ADF4116 540 MHz Output
ADF4117 900 MHz Output
ADF4118 900 MHz Output
ADF4117 836 MHz Output
ADF4118 1750 MHz Output
ADF4118 1750 MHz Output
ADF4118 1960 MHz Output
= 10 MHz; f
DD
(AI
= 10 MHz; f
= 10 MHz; f
= 10 MHz; f
= 10 MHz; f
= 10 MHz; f
= 10 MHz @ 0 dBm).
DD
7
+ DI
DD
= DV
PFD
DD
PFD
PFD
PFD
PFD
PFD
)
= 200 kHz; offset frequency = 1 kHz; f
= 200 kHz; offset frequency = 1 kHz; f
= 30 kHz; offset frequency = 300 Hz; f
= 200 kHz; offset frequency = 1 kHz; f
= 10 kHz; offset frequency = 200 Hz; f
= 200 kHz; offset frequency = 1 kHz; f
6
DD
= 3 V; RF
DD
PFD
/2 bias. See Figure 35 for typical circuit.
: PN
IN
SYNTH
8
for ADF4116 = 540 MHz; RF
10
10
10
11
= PN
9
10
11
10
12
13
14
12
13
14
TOT
– 10logF
B Version
2.7 to 5.5
AV
AV
5.5
5.5
7.5
0.4
1
−213
−89
−87
−90
−78
−85
−65
−84
−88/−99
−90/−104
−91/−100
−80/−84
−88/−90
−65/−73
−80/−86
DD
DD
PFD
to 6.0
– 20logN.
RF
RF
RF
RF
RF
RF
= 540 MHz; N = 2700; loop bandwidth = 20 kHz.
= 900 MHz; N = 4500; loop bandwidth = 20 kHz.
= 836 MHz; N = 27867; loop bandwidth = 3 kHz.
= 1750 MHz; N = 8750; loop bandwidth = 20 kHz.
= 1750 MHz; N = 175000; loop bandwidth = 1 kHz.
= 1960 MHz; N = 9800; loop bandwidth = 20 kHz.
1
IN
for ADF4117, ADF4118 = 900 MHz.
Y Version
2.7 to 5.5
AV
AV
7.5
0.4
1
−213
−89
−87
−90
−78
−85
−65
−84
−88/−99
−90/−104
−91/−100
−80/−84
−88/−90
−65/−73
−80/−86
DD
DD
to 6.0
Rev. D | Page 4 of 28
2
Unit
V min to V max
V min to V max
mA max
mA max
mA max
mA max
μA typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc typ
dBc typ
dBc typ
dBc typ
dBc typ
dBc typ
dBc typ
Test Conditions/Comments
4.5 mA typical
4.5 mA typical
6.5 mA typical
T
@ VCO output
@ 1 kHz offset and 200 kHz PFD frequency
@ 1 kHz offset and 200 kHz PFD frequency
@ 1 kHz offset and 200 kHz PFD frequency
@ 300 Hz offset and 30 kHz PFD frequency
@ 1 kHz offset and 200 kHz PFD frequency
@ 200 Hz offset and 10 kHz PFD frequency
@ 1 kHz offset and 200 kHz PFD frequency
@ 200 kHz/400 kHz and 200 kHz PFD frequency
@ 200 kHz/400 kHz and 200 kHz PFD frequency
@ 200 kHz/400 kHz and 200 kHz PFD frequency
@ 10 kHz/20 kHz and 10 kHz PFD frequency
AV
@ 200 kHz/400 kHz and 200 kHz PFD frequency
@ 30 kHz/60 kHz and 30 kHz PFD frequency
@ 200 kHz/400 kHz and 200 kHz PFD frequency
A
DD
= 25°C
≤ V
TOT
, and subtracting 20logN (where N is the N
P
≤ 6.0 V
IN
for the synthesizer