ADF4156BRUZ-RL Analog Devices Inc, ADF4156BRUZ-RL Datasheet - Page 15

• Manufacturer Part Number: ADF4156BRUZ-RL
• Description: IC,FREQUENCY SYNTHESIZER,CMOS,TSSOP,16PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Type: Fractional N Synthesizer (RF)r

Specifications of ADF4156BRUZ-RL

• Design Resources: Low-Noise Microwave fractional-N PLL using active loop filter and RF prescaler (CN0174)
• Pll: Yes
• Input: CMOS
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 2:1
• Differential - Input:output: Yes/No
• Frequency - Max: 6GHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 2.7 V ~ 3.3 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Frequency-max: 6GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

FUNCTION REGISTER, R3
With the control bits (Bits[2:0]) of Register R2 set to 011, the
on-chip function register is programmed. Figure 20 shows the
input data format for programming this register.
Counter Reset
DB3 is the counter reset bit for the ADF4156. When this bit is
set to 1, the synthesizer counters are held in reset. For normal
operation, this bit should be 0.
Charge-Pump Three-State
When programmed to 1, DB4 puts the charge pump into three-
state mode. This bit should be set to 0 for normal operation.
Power-Down
DB5 on the ADF4156 provides the programmable power-down
mode. Setting this bit to 1 performs a power-down. Setting this
bit to 0 returns the synthesizer to normal operation. While in
software power-down mode, the part retains all information in
its registers. Only when supplies are removed are the register
contents lost.
When a power-down is activated, the following events occur:
1.
2.
3.
4.
5.
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
The synthesizer counters are forced to their load state
conditions.
The charge pump is forced into three-state mode.
The digital lock detect circuitry is reset.
The RF
The input register remains active and capable of loading
and latching data.
0
0
IN
input is debiased.
0
0
0
0
0
RESERVED
0
0
0
0
Figure 20. Function Register (R3) Map
0
0
Rev. A | Page 15 of 24
0
0
U12
0
1
0
Σ-Δ
ENABLED
DISABLED
Phase Detector Polarity
DB6 in the ADF4156 sets the phase detector polarity. When the
VCO characteristics are positive, this bit should be set to 1.
When the characteristics are negative, DB6 should be set to 0.
Note that the cycle slip reduction function cannot be used if the
phase detector polarity is set to negative.
Lock Detect Precision (LDP)
When DB7 is programmed to 0, the digital lock detect is set
high when the phase error on 40 consecutive phase detector
cycles is less than 10 ns each. When this bit is programmed to 1,
40 consecutive phase detector cycles of less than 6 ns each must
occur before the digital lock detect is set.
Σ-Δ Reset
For most applications, DB14 should be programmed to 0. When
DB14 is programmed to 0, the Σ-Δ modulator is reset to its starting
point, or starting phase word, on every write to Register R0. This
has the effect of producing consistent spur levels.
If it is not required that the Σ-Δ modulator be reset on each
write to Register R0, DB14 should be set to 1.
U12
RESET
0
0
RESERVED
0
0
U10
0
1
U11
0
1
0
PD POLARITY
NEGATIVE
POSITIVE
0
LDP
10ns
6ns
U11 U10
U9
0
1
POWER-DOWN
DISABLED
ENABLED
U9
U8
U8
0
1
U7 C3(0) C2(1) C1(1)
U7
0
1
CP
THREE-STATE
DISABLED
ENABLED
COUNTER
RESET
DISABLED
ENABLED
ADF4156
CONTROL
BITS