ADF4156BRUZ-RL Analog Devices Inc, ADF4156BRUZ-RL Datasheet - Page 9

• Manufacturer Part Number: ADF4156BRUZ-RL
• Description: IC,FREQUENCY SYNTHESIZER,CMOS,TSSOP,16PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Type: Fractional N Synthesizer (RF)r

Specifications of ADF4156BRUZ-RL

• Design Resources: Low-Noise Microwave fractional-N PLL using active loop filter and RF prescaler (CN0174)
• Pll: Yes
• Input: CMOS
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 2:1
• Differential - Input:output: Yes/No
• Frequency - Max: 6GHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 2.7 V ~ 3.3 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Frequency-max: 6GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CLOCK DIVIDER OUTPUT
PHASE FREQUENCY DETECTOR (PFD) AND
CHARGE PUMP
The PFD takes inputs from the R-counter and N-counter and
produces an output proportional to the phase and frequency
difference between them. Figure 14 is a simplified schematic of the
phase frequency detector. The PFD includes a fixed-delay element
that sets the width of the antibacklash pulse, which is typically 3 ns.
This pulse ensures that there is no dead zone in the PFD transfer
function and results in a consistent reference spur level.
MUXOUT AND LOCK DETECT
The output multiplexer on the ADF4156 allows the user to
access various internal points on the chip. The state of
MUXOUT is controlled by M4, M3, M2, and M1 (for details,
see Figure 16). Figure 15 shows the MUXOUT section in block
diagram form.
ANALOG LOCK DETECT
THREE-STATE OUTPUT
DIGITAL LOCK DETECT
SERIAL DATA OUTPUT
+IN
–IN
R-DIVIDER OUTPUT
N-DIVIDER OUTPUT
HI
HI
R-DIVIDER/2
N-DIVIDER/2
DGND
D1
D2
DV
CLR1
CLR2
DD
U2
U1
Figure 14. PFD Simplified Schematic
Q1
Q2
Figure 15. MUXOUT Schematic
UP
DOWN
DELAY
MUX
U3
CONTROL
CHARGE
PUMP
DGND
DV
DD
CP
MUXOUT
Rev. A | Page 9 of 24
INPUT SHIFT REGISTERS
The ADF4156 digital section includes a 5-bit RF R-counter,
a 12-bit RF N-counter, a 12-bit FRAC counter, and a 12-bit
modulus counter. Data is clocked into the 32-bit shift register
on each rising edge of CLOCK. The data is clocked in MSB first.
Data is transferred from the shift register to one of five latches
on the rising edge of LE. The destination latch is determined by
the state of the three control bits (C3, C2, and C1) in the shift
register. These bits are the three LSBs (DB2, DB1, and DB0), as
shown in Figure 2. The truth table for these bits is shown in
Table 6. Figure 16 shows a summary of how the latches are
programmed.
PROGRAM MODES
Table 6 and Figure 16 through Figure 21 show how to set up the
program modes in the ADF4156.
Several settings in the ADF4156 are double buffered, including
the modulus value, phase value, R-counter value, reference doubler,
reference divide-by-2, and current setting. This means that two
events must occur before the part can use a new value for any of
the double buffered settings. The new value must first be latched
into the device by writing to the appropriate register, and then a
new write must be performed on Register R0. For example, after
the modulus value is updated, Register R0 must be written to in
order to ensure that the modulus value is loaded correctly.
Table 6. C3, C2, and C1 Truth Table
C3
0
0
0
0
1
Control Bits
C2
0
0
1
1
0
0
1
0
1
0
C1
Register
Register R0
Register R1
Register R2
Register R3
Register R4
ADF4156