ADF7025BCPZ-RL7 Analog Devices Inc, ADF7025BCPZ-RL7 Datasheet - Page 32

• Manufacturer Part Number: ADF7025BCPZ-RL7
• Description: IC,RF Modulator/Demodulator,LLCC,48PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Specifications of ADF7025BCPZ-RL7

• Frequency: 431MHz ~ 464MHz, 862MHz ~ 870MHz and 902MHz ~ 928MHz
• Data Rate - Maximum: 384kbps
• Modulation Or Protocol: FSK
• Applications: Keyless Entery, Home Automation, Wireless Audio/Video
• Power - Output: -20dBm ~ 13dBm
• Sensitivity: -104dBm
• Voltage - Supply: 2.3 V ~ 3.6 V
• Current - Receiving: 19mA
• Current - Transmitting: 28mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LFCSP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Modulation Type: FSK
• Product Depth (mm): 7mm
• Product Length (mm): 7mm
• Operating Supply Voltage (min): 2.3V
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADF70XXEKZ1 - KIT DEV ADF702X FOR BF533EZKITEVAL-ADF7025DBZ1 - BOARD EVAL ADF7025 902-928MHZ
• Memory Size: -
• Lead Free Status / Rohs Status: Compliant

ADF7025
REGISTER 4—DEMODULATOR SETUP REGISTER
Register 4—Demodulator Setup Register Comments
• Demodulator Mode 1, Demodulator Mode 3, Demodulator Mode 4, and Demodulator Mode 5 are modes that can be activated to allow
• Post_Demod_BW =
• For Mode 5, the Timeout Delay to Lock Threshold = (LOCK_THRESHOLD_SETTING)/SEQ_CLK, where SEQ_CLK is defined in the
the ADF7025 to demodulate data-encoding schemes that have run-length constraints greater than 7.
the data rate.
Register 3—Receiver Clock Register section.
DEMOD MODE
0
1
2
3
4
5
LM2
0
0
0
0
1
1
2
DEMOD_CLK
11
×
LM1
0
0
1
1
0
1
π
×
DL8
0
0
0
.
1
1
DL8
0
1
0
1
X
DL8
F
CUTOFF
MODE5 ONLY
DL7
0
0
0
.
1
1
DEMOD LOCK/SYNC WORD MATCH
SERIAL PORT CONTROL – FREE RUNNING
SERIAL PORT CONTROL – LOCK THRESHOLD
SYNC WORD DETECT – FREE RUNNING
SYNC WORD DETECT – LOCK THRESHOLD
INTERRUPT/LOCK PIN LOCKS THRESHOLD
DEMOD LOCKED AFTER DL8–DL1 BITS
DEMODULATOR LOCK SETTING
...
...
...
...
...
...
...
, where the cutoff frequency (F
DL3
0
0
0
.
1
1
Figure 43. Register 4—Demodulator Setup Register
DL2
0
0
1
.
1
1
DL1
0
1
0
.
0
1
LOCK_THRESHOLD_TIMEOUT
0
1
2
.
254
255
Rev. A | Page 32 of 44
CUTOFF
INT/LOCK PIN
–
–
OUTPUT
OUTPUT
INPUT
–
) of the postdemodulator filter should typically be 0.75 times
POSTDEMODULATOR BW
DS2
0
0
1
1
DS1
0
1
0
1
DEMODULATOR
TYPE
LINEAR DEMODULATOR
CORRELATOR/DEMODULATOR
INVALID
INVALID
ADDRESS
BITS