ADIS16334BMLZ Analog Devices Inc, ADIS16334BMLZ Datasheet - Page 10
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ADIS16334BMLZ
Manufacturer Part Number
ADIS16334BMLZ
Description
Low Profile IMU
Manufacturer
Analog Devices Inc
Series
iMEMS®, iSensor™r
Datasheet
1.ADIS16334BMLZ.pdf
(20 pages)
Specifications of ADIS16334BMLZ
Output Type
Digital - SPI
Sensor Type
Accelerometer, Gyroscope, 3 Axis
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
ADIS16334
BASIC OPERATION
The ADIS16334 is an autonomous system that requires no user
initialization. When it has a valid power supply, it initializes itself
and starts sampling, processing, and loading sensor data into
the output registers at a sample rate of 819.2 SPS. DIO1 pulses
high after each sample cycle concludes. The SPI interface enables
simple integration with many embedded processor platforms,
as shown in Figure 10 (electrical connection) and Table 6 (pin
descriptions).
Table 6. Generic Master Processor Pin Names and Functions
Pin Name
SS
SCLK
MOSI
MISO
IRQ
The ADIS16334 SPI interface supports full-duplex serial
communication (simultaneous transmit and receive) and uses
the bit sequence shown in Figure 14. Table 7 provides a list of
the most common settings that require attention to initialize a
processor’s serial port for the ADIS16334 SPI interface.
Table 7. Generic Master Processor SPI Settings
Processor Setting
Master
SCLK Rate ≤ 2 MHz
SPI Mode 3
MSB First Mode
16-Bit Mode
1
For burst read, SCLK rate ≤ 1 MHz.
SYSTEM
PROCESSOR
SPI MASTER
VDD
DOUT
SCLK
Figure 10. Electrical Connection Diagram
DIN
CS
I/O LINES ARE COMPATIBLE WITH
SCLK
1
MOSI
MISO
NOTES
1. THE DOUT BIT PATTERN REFLECTS THE ENTIRE CONTENTS OF THE REGISTER IDENTIFIED BY [A6:A0]
2. IF R/W = 1 DURING THE PREVIOUS SEQUENCE, DOUT IS NOT DEFINED.
3.3V OR 5V LOGIC LEVELS
IRQ
SS
IN THE PREVIOUS 16-BIT DIN SEQUENCE WHEN R/W = 0.
Function
Slave select
Serial clock
Master output, slave input
Master input, slave output
Interrupt request
Description
The ADIS16334 operates as a slave.
Maximum serial clock rate.
CPOL = 1 (polarity), CPHA = 1 (phase).
Bit sequence.
Shift register/data length.
D15
R/W
D14
A6
D13
A5
6
3
5
4
7
CS
SCLK
DIN
DOUT
DIO1
D12
A4
10
13
D11
A3
ADIS16334
5V
11
14
D10
A2
Figure 14. SPI Communication Bit Sequence
12
15
A1
D9
A0
D8
Rev. 0 | Page 10 of 20
DC7 DC6 DC5 DC4 DC3
D7
D6
D5
READING SENSOR DATA
The ADIS16334 provides two different options for acquiring
sensor data: single register and burst register. A single register
read requires two 16-bit SPI cycles. The first cycle requests the
contents of a register using the bit assignments in Figure 14.
Bit DC7 to Bit DC0 are don’t cares for a read, and then the output
register contents follow on DOUT during the second sequence.
Figure 11 includes three single register reads in succession. In
this example, the process starts with DIN = 0x0400 to request
the contents of XGYRO_OUT, then follows with 0x0600 to
request YGYRO_OUT and 0x0800 to request ZGYRO_OUT.
Full-duplex operation enables processors to use the same 16-bit
SPI cycle to read data from DOUT while requesting the next set
of data on DIN. Figure 12 provides an example of the four SPI
signals when reading XGYRO_OUT in a repeating pattern.
Burst Read Function
The burst read function enables the user to read all output registers
using one command on the DIN line and shortens the stall time
between each 16-bit segment to one SCLK cycle (see Table 2).
Figure 13 provides the burst read sequence of data on each SPI
signal. The sequence starts with writing 0x3E00 to DIN, followed
by each output register clocking out on DOUT, in the order in
which they appear in Table 8.
DOUT
SCLK
DIN
DOUT
CS
SCLK
D4
DOUT
DIN
DIN
CS
DOUT = 1111 1001 1101 1010 = 0xF9DA = –1574 LSBs => –78.70°/sec
D3
Figure 12. Example SPI Read, Second 16-Bit Sequence
DC2 DC1 DC0
D2
0x0400
0x3E00
1
D1
Figure 13. Burst Read Sequence
Figure 11. SPI Read Example
D0
XGYRO_OUT
XGYRO_OUT
0x0600
2
DON’T CARE
DIN = 0000 0100 0000 0000 = 0x0400
D15
R/W
YGYRO_OUT
YGYRO_OUT
0x0800
3
D14
A6
D13
A5
ZGYRO_OUT
TEMP_OUT
8