ADM1060ARUZ-REEL7 Analog Devices Inc, ADM1060ARUZ-REEL7 Datasheet - Page 18

• Manufacturer Part Number: ADM1060ARUZ-REEL7
• Description: Communications SupvSeq Circuit I.C.
• Manufacturer: Analog Devices Inc
• Type: Sequencerr

Specifications of ADM1060ARUZ-REEL7

• Number Of Voltages Monitored: 7
• Output: Programmable
• Voltage - Threshold: Adjustable/Selectable
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Reset: -
• Reset Timeout: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADM1060
WATCHDOG FAULT DETECTOR
The ADM1060 has a watchdog fault detector. This can be used
to monitor a processor clock to ensure normal operation. The
detector monitors the WDI pin, expecting a low-to-high or
high-to-low transition within a preprogrammed period. The
watchdog timeout period can be programmed from 200 ms to a
maximum of 12.8 sec.
If no transition is detected, two signals are asserted. One is a
latched high signal, indicating a fault has occurred. The other
signal is a low-high-low pulse that can be used as a RESET sig-
nal for a processor core. The width of this pulse can be
programmed from 10 µs to a maximum of 10 ms. These two
Table 20. Watchdog Fault Detector Registers
Hex Address
9C
Table 21. WDCFG Register 0x9C (Power-On Default 0x00)
Bit
7−5
4−3
2–0
Name
Reserved
PULS1−PULS0
PER2−PER0
Table
Table 21
R/W
R/W
R/W
R/W
Name
WDCFG
Description
Unused
Length of Pulse Output once
the Watchdog Detector has
Timed Out
Watchdog Timeout Period
Default Power-On Value
0x00
Rev. B | Page 18 of 52
Description
Program Length Watchdog Timeout and Length of Pulsed Output
PULS1
0
0
1
1
PER2
0
0
0
0
1
1
1
1
watchdog signals can be selected as inputs to each of the PLBs
(see the PLBA section). They can also be inverted, if required;
for example, if a high-low-high pulse were required by a proces-
sor to reset. Thus, a fault on the watchdog can be used to
generate a pulsed or latched output on any or all of the nine
PDOs.
The latched signal can be cleared low by reading LATF1, then
LATF2 across the SMBus interface (see the Fault Registers sec-
tion). The RAM register list and the bit map for the watchdog
fault detector are shown below.
PULS0
0
1
0
1
PER1
0
0
1
1
0
0
1
1
Pulse Length Selected (µs)
10
100
1,000
10,000
PER0
0
1
0
1
0
1
0
1
Watchdog Timeout Selected (ms)
Disabled
200
400
800
1,600
3,200
6,400
12,800