ADM1060ARUZ-REEL7 Analog Devices Inc, ADM1060ARUZ-REEL7 Datasheet - Page 46

• Manufacturer Part Number: ADM1060ARUZ-REEL7
• Description: Communications SupvSeq Circuit I.C.
• Manufacturer: Analog Devices Inc
• Type: Sequencerr

Specifications of ADM1060ARUZ-REEL7

• Number Of Voltages Monitored: 7
• Output: Programmable
• Voltage - Threshold: Adjustable/Selectable
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Reset: -
• Reset Timeout: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADM1060
BLOCK READ
In this operation, the master device reads a block of data from a
slave device. The start address for a block read must previously
have been set. In the case of the ADM1060, this is done by a
Send Byte operation to set a RAM address, or a Write
Byte/Word operation to set an EEPROM address. The block
read operation itself consists of a Send Byte operation that
sends a block read command to the slave, immediately followed
by a repeated start and a read operation that reads out multiple
data bytes, as follows:
1. The master device asserts a START condition on SDA.
2. The master sends the 7-bit slave address followed by the
3. The addressed slave device asserts ACK on SDA.
4. The master sends a command code that tells the slave device
5. The slave asserts ACK on SDA.
6. The master asserts a repeat start condition on SDA.
7. The master sends the 7-bit slave address followed by the
8. The slave asserts ACK on SDA.
9. The ADM1060 sends a byte count data byte that tells the
10. The master asserts ACK on SDA.
11. The master receives 32 data bytes.
12. The master asserts ACK on SDA after each data byte.
13. The master asserts a STOP condition on SDA to end the
1
S
ADDRESS
write bit (low).
to expect a block read. The ADM1060 command code for a
block read is 0xFD (1111 1101 binary).
read bit (high).
master how many data bytes to expect. The ADM1060 will
always return 32 data bytes (0x20), which is the maximum
allowed by the SMBus 1.1 specification.
transaction.
SLAVE
2
W A
Figure 35. Block Read from EEPROM or RAM
3
COMMAND 0xFD
(BLOCK READ)
4
5 6
A S
ADDRESS
SLAVE
7
R A
8
COUNT
BYTE
9
10
A
DATA 1
DATA
11
32
12
A
13 14
A
Rev. B | Page 46 of 52
P
ERROR CORRECTION
The ADM1060 provides the option of issuing a PEC (packet
error correction) byte after a write to RAM, a write to
EEPROM, a block write to RAM/EEPROM, or a block read
from RAM/EEPROM. This enables the user to verify that the
data received by or sent from the ADM1060 is correct. The PEC
byte is an optional byte sent after the last data byte has been
written to or read from the ADM1060. The protocol is as
follows:
1. The ADM1060 issues a PEC byte to the master. The master
2. A NACK is generated after the PEC byte to signal the end of
Note: The PEC byte is calculated using CRC-8. The Frame
Check Sequence (FCS) conforms to CRC-8 by the polynomial
Consult the SMBus 1.1 specification for more information. An
example of a block read with the optional PEC byte is shown in
Figure 36.
1
S
should check the PEC byte and issue another block read if the
PEC byte is incorrect.
the read.
ADDRESS
SLAVE
2
Figure 36. Block Read from EEPROM or RAM with PEC
W A
3
COMMAND 0xFD
(BLOCK READ)
C(x) = x
4
A S
5 6
8
+ x
ADDRESS
2
SLAVE
+ x
7
1
+ 1
R A
8
COUNT
BYTE
9
DATA
32
10
A
A
DATA 1
11
PEC
13
12
A
14
A
15
P