ADM1060ARUZ-REEL7 Analog Devices Inc, ADM1060ARUZ-REEL7 Datasheet - Page 6

• Manufacturer Part Number: ADM1060ARUZ-REEL7
• Description: Communications SupvSeq Circuit I.C.
• Manufacturer: Analog Devices Inc
• Type: Sequencerr

Specifications of ADM1060ARUZ-REEL7

• Number Of Voltages Monitored: 7
• Output: Programmable
• Voltage - Threshold: Adjustable/Selectable
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Reset: -
• Reset Timeout: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADM1060
Parameter
DIGITAL INPUTS (GPI 1–4, WDI, A0, A1)
SERIAL BUS DIGITAL INPUTS (SDA, SCL)
PROGRAMMABLE DELAY BLOCK
WATCHDOG TIMER INPUT
EEPROM RELIABILITY
SERIAL BUS TIMING
NOTES
1
2
3
4
5
6
7
8
At least one VPn must be ≥3.0 V if used as supply. VH must be ≥4.5 V if used as supply.
Specification is not production tested, but is supported by characterization data at initial product release.
1% threshold accuracy is only achievable on parts preprogrammed by Analog Devices. Contact
Logic inputs will accept input high voltages up to 5.5 V even when the device is operating at supply voltages below 5 V.
Endurance is qualified to 100,000 cycles as per JEDEC Std. 22 method A117, and measured at −40°C, +25°C, and +85°C.
For programming and erasing of EEPROM, a minimum V
Retention lifetime equivalent at junction temperature (T
Timing specifications are tested at logic levels of V
Input High Voltage, V
Input Low Voltage, V
Input High Current, I
Input Low Current, I
Input Capacitance
Programmable Pull-Down Current, I
Timeout
Timeout
Endurance
Data Retention
Clock Frequency, f
Glitch Immunity, t
Bus Free Time, t
Start Setup Time, t
Start Hold Time, t
SCL Low Time, t
SCL High Time, t
SCL, SDA Rise Time, t
SCL, SDA Fall Time, t
Data Setup Time, t
Data Hold Time, t
Input High Voltage, V
Input Low Voltage, V
Output Low Voltage, V
5, 6
7
BUF
LOW
HIGH
8
HD;DAT
HD;STA
SW
SCLK
SU;DAT
SU;STA
IL
f
IL
IH
r
IH
IL
IH
OL
4
PULLDOWN
IL
= 0.8 V for a falling edge and V
DD
J
) = 55°C as per JEDEC Std. 22 method A117.
= 3.0 V is required 0°C to +85°C and a minimum V
Min
2.0
–1
2.0
0
0
100
10
4.7
4.7
4
4.7
4
250
300
Rev. B | Page 6 of 52
Typ
10
10
IH
= 2.0 V for a rising edge.
Max
0.8
1
0.8
0.4
500
12.8
400
50
1000
300
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Unit
s
V
V
µA
µA
pF
µA
V
V
V
ms
Kcycles
Years
kHz
ns
µs
µs
µs
µs
µs
ns
µs
ns
ns
DD
Test Conditions/Comments
V
V
If known logic state required
I
16 programmable options on both rising and
falling edge
Eight programmable timeout options
See Figure 27
See Figure 27
See Figure 27
See Figure 27
See Figure 27
See Figure 27
See Figure 27
See Figure 27
See Figure 27
See Figure 27
See Figure 27
OUT
= 4.5 V is required −40°C to 0°C.
IN
IN
= 5.5 V
= 0 V
= −3.0 mA
for further details.