ADP1653ACPZ-R7 Analog Devices Inc, ADP1653ACPZ-R7 Datasheet - Page 5

• Manufacturer Part Number: ADP1653ACPZ-R7
• Description: IC,Laser Diode/LED Driver,LLCC,16PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Type: Photo Flash LEDr

Specifications of ADP1653ACPZ-R7

• Topology: PWM, Step-Up (Boost)
• Number Of Outputs: 1
• Internal Driver: Yes
• Type - Primary: Flash/Torch
• Frequency: 1.2MHz
• Voltage - Supply: 3 V ~ 5.5 V
• Mounting Type: Surface Mount
• Package / Case: 16-LFCSP
• Operating Temperature: -40°C ~ 125°C
• Current - Output / Channel: 200mA, 500mA
• Internal Switch(s): Yes
• Efficiency: 92%
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Output: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADP1653ACPZ-R7TR

I
Table 2.
Parameter
f
t
t
t
t
t
t
t
t
t
t
t
C
1
2
SCL
2
HIGH
LOW
SU, DAT
HD, DAT
SU, STA
HD, STA
BUF
SU, STO
R
F
SP
A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the V
SCL falling edge.
C
B
C TIMING SPECIFICATIONS
B
2
is the total capacitance of one bus line in picofarads.
T
1
SDA
SCL
S = START CONDITION
Sr = REPEATED START CONDITION
P = STOP CONDITION
Min
0.6
1.3
100
0
0.6
0.6
1.3
0.6
20 + 0.1 C
20 + 0.1 C
0
S
t
B
B
LOW
B
B
Max
400
0.9
300
300
50
400
t
R
t
HD, DAT
t
SU, DAT
Unit
kHz
μs
μs
ns
μs
μs
μs
μs
μs
ns
ns
ns
pF
Figure 3. I
t
HIGH
Description
SCL clock frequency
SCL high time
SCL low time
Data setup time
Data hold time
Setup time for repeated start
Hold time for start/repeated start
Bus free time between a stop and a start condition
Setup time for stop condition
Rise time of SCL and SDA
Fall time of SCL and SDA
Pulse width of suppressed spike
Capacitive load for each bus line
Rev. B | Page 5 of 24
2
C Interface Timing Diagram
t
t
F
SU, STA
t
F
Sr
IH
minimum of the SCL signal) to bridge the undefined region of the
t
HD, STA
t
SP
t
SU, STO
t
R
P
t
BUF
S
ADP1653