ADSP-21062LKS-133 Analog Devices Inc, ADSP-21062LKS-133 Datasheet - Page 41

• Manufacturer Part Number: ADSP-21062LKS-133
• Description: Digital Signal Processor(DSP) IC
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21062LKS-133

• Rohs Status: RoHS non-compliant
• Interface: Host Interface, Link Port, Serial Port
• Clock Rate: 33MHz
• Non-volatile Memory: External
• On-chip Ram: 256kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 240-MQFP, 240-PQFP
• Device Core Size: 32b
• Architecture: Super Harvard
• Format: Floating Point
• Clock Freq (max): 33MHz
• Mips: 33
• Device Input Clock Speed: 33MHz
• Ram Size: 256KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.15V
• Operating Supply Voltage (max): 3.45V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: MQFP
• Lead Free Status / Rohs Status: Not Compliant

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
TRANSMIT
LINK PORT ENABLE/THREE-STATE DELAY FROM INSTRUCTION
RECEIVE
LACK (OUT)
LINK PORT INTERRUPT SETUP TIME
LDAT(3:0)
LDAT(3:0)
LACK (IN)
LDAT(3:0)
LCLK 1x
LCLK 2x
LCLK 1x
LCLK 2x
LCLK
LACK
CLKIN
CLKIN
CLKIN
CLKIN
OR
LCLK
LACK
OR
LINK PORT ENABLE OR THREE-STATE TAKES EFFECT 2 CYCLES AFTER A WRITE TO A LINK PORT CONTROL REGISTER.
THE
t
t
SLACH
t
t
ENDLK
DLCLK
DLAHC
OUT
t
t
REQUIREMENT APPLIES TO THE RISING EDGE OF LCLK ONLY FOR THE FIRST NIBBLE TRANSMITTED.
HLDCH
LCLKTWH
t
DLDCH
t
LCLKRWH
t
LCLKTWL
t
SLCK
t
SLDCL
t
IN
HLCK
t
LCLKIW
TRANSMITTED
LAST NIBBLE
Rev. F | Page 41 of 64 | March 2008
t
HLDCL
Figure 24. Link Ports—Receive
t
t
SLACH
LCLKRWL
t
TDLK
TRANSMITTED
FIRST NIBBLE
t
HLACH
t
DLALC
LCLK INACTIVE
(HIGH)
t
DLACLK