ADSP-21065LKCAZ264 Analog Devices Inc, ADSP-21065LKCAZ264 Datasheet - Page 16
![ADSP-21065L 66MHZ MINI BGA](/photos/6/71/67188/bc-196-2_sml.jpg)
ADSP-21065LKCAZ264
Manufacturer Part Number
ADSP-21065LKCAZ264
Description
ADSP-21065L 66MHZ MINI BGA
Manufacturer
Analog Devices Inc
Series
SHARC®r
Type
Fixed/Floating Pointr
Datasheet
1.ADSP-21065LKSZ-240.pdf
(44 pages)
Specifications of ADSP-21065LKCAZ264
Interface
Host Interface, Serial Port
Clock Rate
60MHz
Non-volatile Memory
External
On-chip Ram
64kB
Voltage - I/o
3.30V
Voltage - Core
3.30V
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
196-CSPBGA
Device Core Size
32b
Architecture
Enhanced Harvard
Format
Floating Point
Clock Freq (max)
66MHz
Mips
66
Device Input Clock Speed
66MHz
Ram Size
68KB
Program Memory Size
Not RequiredKB
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3.13V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
196
Package Type
CSPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ADSP-21065LKCAZ264
Manufacturer:
Analog Devices Inc
Quantity:
10 000
ADSP-21065L
Memory Read—Bus Master
Use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) without reference to CLKIN.
These specifications apply when the ADSP-21065L is the bus master when accessing external memory space. These switching
characteristics also apply for bus master synchronous read/write timing (see Synchronous Read/Write—Bus Master below). If these
timing requirements are met, the synchronous read/write timing can be ignored (and vice versa). An exception to this is the ACK pin
timing requirements as described in the note below.
Parameter
Timing Requirements:
t
t
t
t
t
t
Switching Characteristics:
t
t
t
t
t
W = (number of wait states specified in WAIT register) ¥ t
HI = t
H = t
NOTES
1
2
3
Data Delay/Setup: User must meet t
The falling edge of MSx, SW, BMS, are referenced.
ACK is not sampled on external memory accesses that use the Internal wait state mode. For the first CLKIN cycle of a new external memory access, ACK must be
DAD
DRLD
HDA
HDRH
DAAK
DSAK
DRHA
DARL
RW
RWR
RDGL
valid by t
subsequent cycles of a wait stated external memory access, synchronous specifications t
(Both, after internal wait states have completed).
CK
CK
(if an address hold cycle occurs as specified in WAIT register; otherwise H = 0).
(if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
DAAK
ADDRESS
or t
MSx , SW
DMAG
DSAK
Address, Selects Delay to Data Valid
RD Low to Data Valid
Data Hold from Address Selects
Data Hold from RD High
ACK Delay from Address, Selects
ACK Delay from RD Low
Address, Selects Hold After RD High
Address, Selects to RD Low
RD Pulsewidth
RD High to WR, RD Low
RD High to DMAGx Low
DATA
BMS
ACK
WR
RD
or synchronous specification t
DAD
or to t
t
DARL
1
DRLD
3
t
3
DAAK
or synchronous specification t
SACKC
2
Figure 11. Memory Read—Bus Master
CK
3
for wait state modes External, Either, or Both (Both, if the internal wait state is zero). For the second and
.
2, 3
t
DSAK
t
1, 2
DAD
t
DRLD
–16–
SSDATI
t
RW
SACKC
.
and t
Min
0.0
0.0
–1.0 + H
3.0 + 6 DT
25.0 + 26 DT + W
4.5 + 6 DT + HI
11.0 +12 DT + HI
HACKC
must be met for wait state modes External, Either, or Both
t
Max
28.0 + 32 DT + W
24.0 + 26 DT + W
24.0 + 30 DT + W
19.5 + 24 DT + W
HDRH
t
HDA
t
DRHA
t
t
RWR
RDGL
REV. C
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns