ADSP-21065LKCAZ264 Analog Devices Inc, ADSP-21065LKCAZ264 Datasheet - Page 8
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ADSP-21065LKCAZ264
Manufacturer Part Number
ADSP-21065LKCAZ264
Description
ADSP-21065L 66MHZ MINI BGA
Manufacturer
Analog Devices Inc
Series
SHARC®r
Type
Fixed/Floating Pointr
Datasheet
1.ADSP-21065LKSZ-240.pdf
(44 pages)
Specifications of ADSP-21065LKCAZ264
Interface
Host Interface, Serial Port
Clock Rate
60MHz
Non-volatile Memory
External
On-chip Ram
64kB
Voltage - I/o
3.30V
Voltage - Core
3.30V
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
196-CSPBGA
Device Core Size
32b
Architecture
Enhanced Harvard
Format
Floating Point
Clock Freq (max)
66MHz
Mips
66
Device Input Clock Speed
66MHz
Ram Size
68KB
Program Memory Size
Not RequiredKB
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3.13V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
196
Package Type
CSPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ADSP-21065LKCAZ264
Manufacturer:
Analog Devices Inc
Quantity:
10 000
ADSP-21065L
Pin
HBR
HBG
CS
REDY (O/D)
DMAR
DMAR
DMAG
DMAG
BR
ID
CPA (O/D)
DTxX
DRxX
TCLKx
RCLKx
TFSx
RFSx
BSEL
1-0
2-1
1
2
1
2
Type
I/A
I/O
I/A
O
I/A
I/A
O/T
O/T
I/O/S
I
I/O
O
I
I/O
I/O
I/O
I/O
I
Function
Host Bus Request. Must be asserted by a host processor to request control of the ADSP-
21065L’s external bus. When HBR is asserted in a multiprocessing system, the ADSP-21065L
that is bus master will relinquish the bus and assert HBG. To relinquish the bus, the ADSP-
21065L places the address, data, select, and strobe lines in a high impedance state. It does,
however, continue to drive the SDRAM control pins. HBR has priority over all ADSP-21065L
bus requests (BR
Host Bus Grant. Acknowledges an HBR bus request, indicating that the host processor may
take control of the external bus. HBG is asserted by the ADSP-21065L until HBR is released.
In a multiprocessor system, HBG is output by the ADSP-21065L bus master.
Chip Select. Asserted by host processor to select the ADSP-21065L.
Host Bus Acknowledge. The ADSP-21065L deasserts REDY to add wait states to an asyn-
chronous access of its internal memory or IOP registers by a host. Open drain output (O/D) by
default; can be programmed in ADREDY bit of SYSCON register to be active drive (A/D).
REDY will only be output if the CS and HBR inputs are asserted.
DMA Request 1 (DMA Channel 9).
DMA Request 2 (DMA Channel 8).
DMA Grant 1 (DMA Channel 9).
DMA Grant 2 (DMA Channel 8).
Multiprocessing Bus Requests. Used by multiprocessing ADSP-21065Ls to arbitrate for bus
mastership. An ADSP-21065L drives its own BRx line (corresponding to the value of its ID
inputs) only and monitors all others. In a uniprocessor system, tie both BRx pins to VDD.
Multiprocessing ID. Determines which multiprocessor bus request (BR
ADSP-21065L. ID = 01 corresponds to BR
processor systems. These lines are a system configuration selection which should be hard-wired
or changed only at reset.
Core Priority Access. Asserting its CPA pin allows the core processor of an ADSP-21065L
bus slave to interrupt background DMA transfers and gain access to the external bus. CPA is an
open drain output that is connected to both ADSP-21065Ls in the system. The CPA pin has an
internal 5 kW pull-up resistor. If core access priority is not required in a system, leave the CPA
pin unconnected.
Data Transmit (Serial Ports 0, 1; Channels A, B). Each DTxX pin has a 50 kW internal pull-
up resistor.
Data Receive (Serial Ports 0, 1; Channels A, B). Each DRxX pin has a 50 kW internal pull-up
resistor.
Transmit Clock (Serial Ports 0, 1). Each TCLK pin has a 50 kW internal pull-up resistor.
Receive Clock (Serial Ports 0, 1). Each RCLK pin has a 50 kW internal pull-up resistor.
Transmit Frame Sync (Serial Ports 0, 1).
Receive Frame Sync (Serial Ports 0, 1).
EPROM Boot Select. When BSEL is high, the ADSP-21065L is configured for booting from
an 8-bit EPROM. When BSEL is low, the BSEL and BMS inputs determine booting mode. See
BMS for details. This signal is a system configuration selection which should be hardwired.
2-1
) in a multiprocessor system.
–8–
1
, ID = 10 corresponds to BR
1
2
–BR
. ID = 00 in single-
2
) is used by
REV. C
2-0