ADSP-BF514BBCZ-4F4 Analog Devices Inc, ADSP-BF514BBCZ-4F4 Datasheet - Page 6

• Manufacturer Part Number: ADSP-BF514BBCZ-4F4
• Description: Low-Pwr BF Proc W/flash & Cnsmr Conctvty
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF514BBCZ-4F4

• Interface: I²C, PPI, RSI, SPI, SPORT, UART/USART
• Clock Rate: 400MHz
• Non-volatile Memory: FLASH (4Mbit)
• On-chip Ram: 116kB
• Voltage - I/o: 1.8V, 2.5V, 3.3V
• Voltage - Core: 1.30V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 168-LFBGA
• Architecture: Modified Harvard
• Format: Fixed Point
• Clock Freq (max): 400MHz
• Device Input Clock Speed: 400MHz
• Ram Size: 48KB
• Program Memory Size: 1024KB
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Package: 168CSP-BGA
• Numeric And Arithmetic Format: Fixed-Point
• Maximum Speed: 400 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
The asynchronous memory controller can be programmed to
control up to four banks of devices with very flexible timing
parameters for a wide variety of devices. Each bank occupies a
1M byte segment regardless of the size of the devices used, so
that these banks are only contiguous if each is fully populated
with 1M byte of memory.
Flash Memory
The ADSP-BF512F/ADSP-BF514F/ADSP-BF516F/
ADSP-BF518F processors contain a SPI flash memory within
the package of the processor and connected to SPI0
The SPI flash memory has a 4M bit capacity and 1.8V (nominal)
operating voltage. The program/erase endurance is 100,000
cycles per block, and this memory has greater than 100 years
data retention capability. Also included are support for software
write protection and support for fast erase and byte-program.
The processors internally connect to the flash memory die with
the SPI0SCK, SPI0SEL4 or PH8, SPI0MOSI, and SPI0MISO sig-
nals similar to an external SPI flash (for signal descriptions, see
Table 2 on Page
ronment, these internally connected signals are not exposed
outside of the package. For this reason, programming the
ADSP-BF51xF flash memory is performed by running code on
7). To further provide a secure processing envi-
Combinational Logic
ADSP-BF51xF
Package
ADSP-BF51x Die
Truth Table
SPI0
SPICLK
MISO
MOSI
1
0
Signals between the processor and the flash
operate at the VDDFLASH voltage level.
or PH8
MISO_EXT, SPICLK_EXT, MOSI_EXT
Three-state
As programmed
MISO_INT
SPICLK_INT
MOSI_INT
Rev. A | Page 6 of 72 | August 2010
(Figure
Figure 3. Flash Memory Block Diagram
Combinational Logic
3).
SPICLK_EXT
SO
SCK
SI
PH8
MISO_EXT
MOSI_EXT
the processor. It cannot be programmed from external signals
and data transfers between the SPI flash and the processor can-
not be probed externally. The Flash memory has the following
additional features
SPI Flash Die
• Serial Interface Architecture—SPI compatible with Mode 0
• Superior Reliability—Endurance of 100,000 cycles and
• Flexible Erase Capability—Uniform 4K Byte sectors and
• Fast Erase and Byte-Program—Chip-erase time = 125 ms
• Auto Address Increment (AAI) Programming—Decreases
• End-of-Write Detection—Software polling the BUSY bit in
• Software Write Protection—Write protection through
and Mode 3
greater than 100 years data retention
uniform 32 and 64K Byte overlay blocks
(typical), Sector-/Block-Erase Time = 62 ms (typical) Byte-
Program Time = 50 μS (typical)
total chip programming time over byte-program
operations
status register, busy status readout on SO pin
block-protection bits in status register
GND
VDD
M
U
X
L
O
G
I
C
PG13-SPI0MISO
PG12-SPI0SCK
PG14-SPI0MOSI
PG11-
VDDFLASH
GND
SPI0 signals external
to the processor
operate at the
VDDEXT voltage
level.