ADSP-BF514BBCZ-4F4 Analog Devices Inc, ADSP-BF514BBCZ-4F4 Datasheet - Page 7

• Manufacturer Part Number: ADSP-BF514BBCZ-4F4
• Description: Low-Pwr BF Proc W/flash & Cnsmr Conctvty
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF514BBCZ-4F4

• Interface: I²C, PPI, RSI, SPI, SPORT, UART/USART
• Clock Rate: 400MHz
• Non-volatile Memory: FLASH (4Mbit)
• On-chip Ram: 116kB
• Voltage - I/o: 1.8V, 2.5V, 3.3V
• Voltage - Core: 1.30V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 168-LFBGA
• Architecture: Modified Harvard
• Format: Fixed Point
• Clock Freq (max): 400MHz
• Device Input Clock Speed: 400MHz
• Ram Size: 48KB
• Program Memory Size: 1024KB
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Package: 168CSP-BGA
• Numeric And Arithmetic Format: Fixed-Point
• Maximum Speed: 400 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 2. Internal Flash Memory Signal Descriptions
One-Time Programmable Memory
The processors have 64K bits of one-time programmable non-
volatile memory that can be programmed by the developer only
one time. It includes the array and logic to support read access
and programming. Additionally, its pages can be write
protected.
OTP enables developers to store both public and private data
on-chip. In addition to storing public and private key data for
applications requiring security, it also allows developers to store
completely user-definable data such as customer ID, product
ID, and MAC address. Hence generic parts can be shipped
which are then programmed and protected by the developer
within this non-volatile memory.
I/O Memory Space
The processors do not define a separate I/O space. All resources
are mapped through the flat 32-bit address space. On-chip I/O
devices have their control registers mapped into memory-
mapped registers (MMRs) at addresses near the top of the
4G byte address space. These are separated into two smaller
blocks, one which contains the control MMRs for all core func-
tions, and the other which contains the registers needed for
setup and control of the on-chip peripherals outside of the core.
The MMRs are accessible only in supervisor mode and appear
as reserved space to on-chip peripherals.
Booting
The processors contain a small on-chip boot kernel, which con-
figures the appropriate peripheral for booting. If the processors
are configured to boot from boot ROM memory space, the pro-
cessor starts executing from the on-chip boot ROM. For more
information, see
Event Handling
The event controller handles all asynchronous and synchronous
events to the processor. The processors provide event handling
that supports both nesting and prioritization. Nesting allows
multiple event service routines to be active simultaneously.
Symbol
SCK
SI
SO
CE
RST
ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
Booting Modes on Page
Pin Name
Serial Clock
Serial Data Input
Serial Data Output
Chip Enable
Reset
18.
Provides the timing of the serial interface.
Transfers data serially out of the device.
Function
Commands, addresses, or input data are latched on the rising edge of the clock input, while
output data is shifted out on the falling edge of the clock input.
Transfers commands, addresses, or data serially into the device.
Inputs are latched on the rising edge of the serial clock.
Data is shifted out on the falling edge of the serial clock.
Flash busy status pin in AAI mode if SO is configured as a hardware RY/BY pin.
The device is enabled by a high to low transition on CE. CE must remain low for the duration
of any command sequence.
Resets the operation of the device and the internal logic. This signal is tied to the ADSP-BF51x
RESET signal.
Rev. A | Page 7 of 72 | August 2010
Prioritization ensures that servicing of a higher priority event
takes precedence over servicing of a lower priority event. The
controller provides support for five different types of events:
Each event type has an associated register to hold the return
address and an associated return-from-event instruction. When
an event is triggered, the state of the processor is saved on the
supervisor stack.
The event controller consists of two stages, the core event con-
troller (CEC) and the system interrupt controller (SIC). The
core event controller works with the system interrupt controller
to prioritize and control all system events. Conceptually, inter-
rupts from the peripherals enter into the SIC, and are then
routed directly into the general-purpose interrupts of the CEC.
• Emulation—An emulation event causes the processor to
• Reset—This event resets the processor.
• Nonmaskable Interrupt (NMI)—The NMI event can be
• Exceptions—Events that occur synchronously to program
• Interrupts—Events that occur asynchronously to program
enter emulation mode, allowing command and control of
the processor through the JTAG interface.
generated by the software watchdog timer or by the NMI
input signal to the processor. The NMI event is frequently
used as a power-down indicator to initiate an orderly shut-
down of the system.
flow; that is, the exception is taken before the instruction is
allowed to complete. Conditions such as data alignment
violations and undefined instructions cause exceptions.
flow. They are caused by input signals, timers, and other
peripherals, as well as by an explicit software instruction.