ADSP-BF514KBCZ-4F4 Analog Devices Inc, ADSP-BF514KBCZ-4F4 Datasheet - Page 53

• Manufacturer Part Number: ADSP-BF514KBCZ-4F4
• Description: Low-Pwr BF Proc W/flash & Cnsmr Conctvty
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF514KBCZ-4F4

• Interface: I²C, PPI, RSI, SPI, SPORT, UART/USART
• Clock Rate: 400MHz
• Non-volatile Memory: FLASH (4Mbit)
• On-chip Ram: 116kB
• Voltage - I/o: 1.8V, 2.5V, 3.3V
• Voltage - Core: 1.30V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 168-LFBGA
• Architecture: Modified Harvard
• Format: Fixed Point
• Clock Freq (max): 400MHz
• Device Input Clock Speed: 400MHz
• Ram Size: 48KB
• Program Memory Size: 1024KB
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Output Disable Time Measurement
Output signals are considered to be disabled when they stop
driving, go into a high impedance state, and start to decay from
their output high or low voltage. The output disable time t
the difference between t
left side of
The time for the voltage on the bus to decay by ΔV is dependent
on the capacitive load C
time can be approximated by the equation:
The time t
ΔV equal to 0.25 V for V
and 0.15 V for V
The time t
signal switches to when the output voltage decays ΔV from the
measured output high or output low voltage.
Example System Hold Time Calculation
To determine the data output hold time in a particular system,
first calculate t
to be the difference between the ADSP-BF51x processor’s out-
put voltage and the input threshold for the device requiring the
hold time. C
the total leakage or three-state current (per data line). The hold
time is t
in the
an SDRAM write cycle as shown in
on Page
Capacitive Loading
Output delays and holds are based on standard capacitive loads
of an average of 6 pF on all balls (see
to (V
Figure 67
The delay and hold specifications given should be derated by a
factor derived from these figures. The graphs in these figures
may not be linear outside the ranges shown.
DDEXT
Timing Specifications on Page 27
DECAY
31).
ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
show how output rise time varies with capacitance.
DECAY
DIS_MEASURED
/V
Figure
L
DDMEM
t
is the total bus capacitance (per data line), and I
plus the various output disable times as specified
DIS
DECAY
is calculated with test loads C
DDEXT
54.
=
)/2. The graphs of
t
using the equation given above. Choose ΔV
DECAY
t
/
DIS_MEASURED
is the interval from when the reference
VDDMEM
DIS_MEASURED
L
DDEXT
and the load current I
=
/V
(nominal) = 1.8 V.
(
DDMEM
C
L
Δ
SDRAM Interface Timing
and t
–
Figure
V
Figure 56
t
(nominal) = 2.5 V/3.3 V
) I
DECAY
(for example t
⁄
DECAY
L
55). V
L
and I
as shown on the
L
through
. This decay
LOAD
Rev. B | Page 53 of 68 | January 2011
L
and with
DSDAT
is equal
DIS
for
L
is
is
V
LOAD
NOTES:
THE WORST CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USED
FOR THE OUTPUT TIMING ANALYSIS TO REFLECT THE TRANSMISSION LINE
EFFECT AND MUST BE CONSIDERED. THE TRANSMISSION LINE (TD) IS FOR
LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS.
ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN
SYSTEM REQUIREMENT. IF NECESSARY, A SYSTEM MAY INCORPORATE
EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES.
4pF
12
10
8
6
4
2
0
Figure 56. Driver Type A Typical Rise and Fall Times (10%–90%) vs.
0
Figure 55. Equivalent Device Loading for AC Measurements
50:
70:
50:
400:
2pF
Load Capacitance (1.8V V
50
(Includes All Fixtures)
45:
0.5pF
LOAD CAPACITANCE (pF)
TESTER PIN ELECTRONICS
100
ZO = 50: (impedance)
TD = 4.04 ± 1.18 ns
DDEXT
150
/V
T1
DDMEM
t
t
t
RISE
RISE
FALL
t
)
FALL
= 1.8V @ 25
= 1.8V @ 25
200
OUTPUT
DUT
° C
° C
250