ADSP-BF514KSWZ-4F4 Analog Devices Inc, ADSP-BF514KSWZ-4F4 Datasheet - Page 49
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ADSP-BF514KSWZ-4F4
Manufacturer Part Number
ADSP-BF514KSWZ-4F4
Description
Low-Pwr BF Proc W/flash & Cnsmr Conctvty
Manufacturer
Analog Devices Inc
Series
Blackfin®r
Type
Fixed Pointr
Datasheets
1.ADSP-BF531SBSTZ400.pdf
(12 pages)
2.ADSP-BF512KSWZ-3.pdf
(68 pages)
3.ADSP-BF514KSWZ-4F4.pdf
(72 pages)
Specifications of ADSP-BF514KSWZ-4F4
Interface
I²C, PPI, RSI, SPI, SPORT, UART/USART
Clock Rate
400MHz
Non-volatile Memory
FLASH (4Mbit)
On-chip Ram
116kB
Voltage - I/o
1.8V, 2.5V, 3.3V
Voltage - Core
1.30V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
176-LQFP Exposed Pad, 176-eLQFP, 176-HLQFP
Architecture
Modified Harvard
Format
Fixed Point
Clock Freq (max)
400MHz
Device Input Clock Speed
400MHz
Ram Size
48KB
Program Memory Size
1024KB
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
176
Package Type
LQFP EP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ADSP-BF514KSWZ-4F4
Manufacturer:
Analog Devices Inc
Quantity:
10 000
JTAG Test And Emulation Port Timing
Table 49
Table 49. JTAG Port Timing
1
2
3
Parameter
Timing Requirements
t
t
t
t
t
t
Switching Characteristics
t
t
System Inputs = DATA15–0, SCL, SDA, TFS0, TSCLK0, RSCLK0, RFS0, DR0PRI, DR0SEC, PF15–0, PG15–0, PH7–0, MDIO, TD1, TMS, RESET, NMI, BMODE2–0.
50 MHz Maximum
System Outputs = DATA15–0, ADDR19–1, ABE1–0, ARE, AWE, AMS1–0, SRAS, SCAS, SWE, SCKE, CLKOUT, SA10, SMS, SCL, SDA, TSCLK0, TFS0, RFS0, RSCLK0,
TCK
STAP
HTAP
SSYS
HSYS
TRSTW
DTDO
DSYS
DT0PRI, DT0SEC, PF15–0, PG15–0, PH7–0, MDC, MDIO.
1
1
3
ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
and
OUTPUTS
SYSTEM
SYSTEM
INPUTS
Figure 37
TCK
TMS
TDO
TDI
TCK Period
TDI, TMS Setup Before TCK High
TDI, TMS Hold After TCK High
System Inputs Setup Before TCK High
System Inputs Hold After TCK High
TRST Pulse Width
TDO Delay from TCK Low
System Outputs Delay After TCK Low
describe JTAG port operations.
2
(measured in TCK cycles)
t
DSYS
t
DTDO
t
TCK
Rev. B | Page 49 of 68 | January 2011
t
SSYS
t
STAP
Figure 37. JTAG Port Timing
t
HTAP
t
HSYS
Min
20
4
4
4
5
4
0
Max
10
13
Unit
ns
ns
ns
ns
ns
TCK
ns
ns