ADUC7023BCPZ62I-RL Analog Devices Inc, ADUC7023BCPZ62I-RL Datasheet - Page 60

• Manufacturer Part Number: ADUC7023BCPZ62I-RL
• Description: Flash ARM7+8-ch,12-B ADC & 4x12-B DAC IC
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7023BCPZ62I-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 44MHz
• Connectivity: I²C, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 12
• Program Memory Size: 62KB (62K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 32-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADuC7023
I
Name:
Address:
Default value:
Access:
Function:
Table 65. I2CxMSTA MMR Bit Designations
Bit
15 to 11
10
9
8
7
6
5
4
3
2
1 to 0
2
C Master Status Registers, I2CxMSTA
Name
I2CBBUSY
I2CMRxFO
I2CMTC
I2CMNA
I2CMBUSY
I2CAL
I2CMNA
I2CMRXQ
I2CMTXQ
I2CMTFSTA
I2C0MSTA , I2C1MSTA
0xFFFF0804, 0xFFFF0904
0x0000, 0x0000
Read
These 16-bit MMRs are the I
Description
Reserved. These bits are reserved.
I
This bit is set to 1 when a start condition is detected on the I
This bit is cleared when a stop condition is detected on the bus.
Master Rx FIFO overflow.
This bit is set to 1 when a byte is written to the Rx FIFO when it is already full.
This bit is cleared in all other conditions.
I
This bit is set to 1 when a transmission is complete between the master and the slave with which it was
communicating. If the I2CMCENI bit in I2CxMCON is set, an interrupt is generated when this bit is set.
This bit clears this interrupt source.
I
This bit is set to 1 when a no acknowledge condition is received by the master in response to a data write
transfer. If the I2CNACKENI bit in I2CxMCON is set, an interrupt is generated when this bit is set.
This bit is cleared in all other conditions.
I
This bit is set to 1 when the master is busy processing a transaction.
This bit is cleared if the master is ready or if another master device has control of the bus.
I
This bit is set to 1 when the I
I2C1MCON is set, an interrupt is generated when this bit is set.
This bit is cleared in all other conditions.
I
This bit is set to 1 when a no acknowledge condition is received by the master in response to an address. If
the I2CNACKENI bit in I2C1MCON is set, an interrupt is generated when this bit is set.
This bit is cleared in all other conditions.
I
This bit is set to 1 when data enters the Rx FIFO. If the I2CMRENI in I2C1MCON is set, an interrupt is
generated.
This bit is cleared in all other conditions.
I
This bit becomes high if the Tx FIFO is empty or only contains one byte and the master has transmitted an
address and write. If the I2CMTENI bit in I2C1MCON is set, an interrupt is generated when this bit is set.
This bit is cleared in all other conditions.
I
00 = I
01 = 1 byte in master Tx FIFO.
10 = 1 byte in master Tx FIFO.
11 = I
2
2
2
2
2
2
2
2
2
C bus busy status bit.
C transmission complete status bit.
C master no acknowledge data bit.
C master busy status bit.
C arbitration lost status bit.
C master no acknowledge address bit.
C master receive request bit.
C master transmit request bit.
C master Tx FIFO status bits.
2
2
C master Tx FIFO empty.
C master Tx FIFO full.
2
C status registers in master mode.
Rev. B | Page 60 of 96
2
C master has lost in trying to gain control of the I
2
C bus.
2
C bus. If the I2CALENI bit in