ADUC7060BSTZ32 Analog Devices Inc, ADUC7060BSTZ32 Datasheet - Page 61

• Manufacturer Part Number: ADUC7060BSTZ32
• Description: DUAL 24-BIT AFE AND ARM 7 I.C
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7060BSTZ32

• Design Resources: 4 mA-to-20 mA Loop-Powered Temperature Monitor Using ADuC7060/1 (CN0145) Low power, Long Range, ISM Wireless Measuring Node (CN0164)
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 10MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 14
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 2.625 V
• Data Converters: A/D 5x24b, 8x24b, D/A 1x14b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-LQFP
• Cpu Family: ADuC7xxx
• Device Core: ARM7TDMI
• Device Core Size: 16/32Bit
• Frequency (max): 10.24MHz
• Interface Type: I2C/SPI/UART
• Total Internal Ram Size: 4KB
• # I/os (max): 14
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 2.5V
• Operating Supply Voltage (max): 2.625V
• Operating Supply Voltage (min): 2.375V
• On-chip Adc: 2(4-chx24-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Package: 48LQFP
• Family Name: ADuC7xxx
• Maximum Speed: 10.24 MHz
• Operating Supply Voltage: 2.5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 14
• Number Of Timers: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Table 68. IRQVEC MMR Bit Designations
Bit
31:23
22:7
6:2
1:0
Priority Registers
The interrupt priority registers, IRQP0, IRQP1, and IRQP2,
allow each interrupt source to have its priority level configured
for a level between 0 and 7. Level 0 is the highest priority level.
IRQP0 Register
Name:
Address:
Default value:
Access:
Table 69. IRQP0 MMR Bit Designations
Bit
31:27
26:24
23
22:20
19
18:16
15
14:12
11:7
6:4
3:0
Access
Read
only
Read
only
Read
only
Reserved
Name
Reserved
T3PI
Reserved
T2PI
Reserved
T1PI
Reserved
T0PI
Reserved
SWINTP
Reserved
IRQP0
0xFFFF0020
0x00000000
Read and write
Initial
Value
0
0
0
0
Description
Reserved bits.
A priority level of 0 to 7 can be set for
Timer3.
Reserved bit.
A priority level of 0 to 7 can be set for
Timer2.
Reserved bit.
A priority level of 0 to 7 can be set for
Timer1.
Reserved bit.
A priority level of 0 to 7 can be set for
Timer0.
Reserved bits.
A priority level of 0 to 7 can be set for the
software interrupt source.
Interrupt 0 cannot be prioritized.
Description
Always read as 0.
IRQBASE register value.
Highest priority IRQ source. This
is a value between 0 to 19 repre-
senting the possible interrupt
sources. For example, if the highest
currently active IRQ is Timer1, then
these bits are [01000].
Reserved bits.
Rev. B | Page 61 of 108
IRQP1 Register
Name:
Address:
Default value:
Access:
Table 70. IRQP1 MMR Bit Designations
Bit
31
30:28
27
26:24
23
22:20
19
18:16
15
14:12
11
10:8
7:0
IRQP2 Register
Name:
Address:
Default value:
Access:
Table 71. IRQP2 MMR Bit Designations
Bit
31:15
14:12
11
10:8
7
6:4
3
2:0
Name
Reserved
I2CMPI
Reserved
IRQ1PI
Reserved
IRQ0PI
Reserved
SPIMPI
Reserved
UARTPI
Reserved
ADCPI
Reserved
Name
Reserved
IRQ3PI
Reserved
IRQ2PI
Reserved
SPISPI
Reserved
I2CSPI
IRQP1
0xFFFF0024
0x00000000
Read and write
IRQP2
0xFFFF0028
0x00000000
Read and write
Description
Reserved bit.
A priority level of 0 to 7 can be set for I
master.
Reserved bit.
A priority level of 0 to 7 can be set for IRQ1.
Reserved bit.
A priority level of 0 to 7 can be set for IRQ0.
Reserved bit.
A priority level of 0 to 7 can be set for SPI
master.
Reserved bit.
A priority level of 0 to 7 can be set for UART.
Reserved bit.
A priority level of 0 to 7 can be set for the
ADC interrupt source.
Reserved bits.
Description
Reserved bit.
A priority level of 0 to 7 can be set for IRQ3.
Reserved bit.
A priority level of 0 to 7 can be set for IRQ2.
Reserved bit.
A priority level of 0 to 7 can be set for SPI
slave.
Reserved bit.
A priority level of 0 to 7 can be set for I
slave.
ADuC7060/ADuC7061
2
2
C
C