ADUC843BSZ62-3 Analog Devices Inc, ADUC843BSZ62-3 Datasheet - Page 60
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ADUC843BSZ62-3
Manufacturer Part Number
ADUC843BSZ62-3
Description
Microconverter, ADUC842 Without DACs
Manufacturer
Analog Devices Inc
Series
MicroConverter® ADuC8xxr
Datasheet
1.EVAL-ADUC842QS.pdf
(88 pages)
Specifications of ADUC843BSZ62-3
Core Processor
8052
Core Size
8-Bit
Speed
8.38MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
DMA, PSM, PWM, Temp Sensor, WDT
Number Of I /o
32
Program Memory Size
62KB (62K x 8)
Program Memory Type
FLASH
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-MQFP, 52-PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ADUC843BSZ62-3
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Part Number:
ADUC843BSZ62-3
Manufacturer:
ADI/亚德诺
Quantity:
20 000
ADuC841/ADuC842/ADuC843
Timers/Counters
The ADuC841/ADuC842/ADuC843 have three 16-bit timer/
counters: Timer 0, Timer 1, and Timer 2. The timer/counter
hardware is included on-chip to relieve the processor core of the
overhead inherent in implementing timer/counter functionality
in software. Each timer/counter consists of two 8-bit registers:
THx and TLx (x = 0, 1, and 2). All three can be configured to
operate either as timers or as event counters.
In timer function, the TLx register is incremented every
machine cycle. Thus, one can think of it as counting machine
cycles. Since a machine cycle on a single-cycle core consists of
one core clock period, the maximum count rate is the core clock
frequency.
In counter function, the TLx register is incremented by a 1-to-0
transition at its corresponding external input pin: T0, T1, or T2.
When the samples show a high in one cycle and a low in the
next cycle, the count is incremented. Since it takes two machine
cycles (two core clock periods) to recognize a 1-to-0 transition,
the maximum count rate is half the core clock frequency.
Table 28. TMOD SFR Bit Designations
Bit No.
7
6
5
4
3
2
1
0
Name
Gate
C/T
M1
M0
Gate
C/T
M1
M0
Description
Timer 1 Gating Control.
Set by software to enable Timer/Counter 1 only while the INT1 pin is high and the TR1 control bit is set.
Cleared by software to enable Timer 1 whenever the TR1 control bit is set.
Timer 1 Timer or Counter Select Bit.
Set by software to select counter operation (input from T1 pin).
Cleared by software to select timer operation (input from internal system clock).
Timer 1 Mode Select Bit 1 (Used with M0 Bit).
Timer 1 Mode Select Bit 0.
M1
0
0
1
1
Timer 0 Gating Control.
Set by software to enable Timer/Counter 0 only while the INT0 pin is high and the TR0 control bit is set.
Cleared by software to enable Timer 0 whenever the TR0 control bit is set.
Timer 0 Timer or Counter Select Bit.
Set by software to select counter operation (input from T0 pin).
Cleared by software to select timer operation (input from internal system clock).
Timer 0 Mode Select Bit 1.
Timer 0 Mode Select Bit 0.
M1
0
0
1
1
M0
0
1
0
1
M0
0
1
0
1
TH1 operates as an 8-bit timer/counter. TL1 serves as 5-bit prescaler.
16-Bit Timer/Counter. TH1 and TL1 are cascaded; there is no prescaler.
8-Bit Autoreload Timer/Counter. TH1 holds a value that is to be reloaded into TL1 each time it
overflows.
Timer/Counter 1 Stopped.
TH0 operates as an 8-bit timer/counter. TL0 serves as a 5-bit prescaler.
16-Bit Timer/Counter. TH0 and TL0 are cascaded; there is no prescaler.
8-Bit Autoreload Timer/Counter. TH0 holds a value that is to be reloaded into TL0 each time it
overflows.
TL0 is an 8-bit timer/counter controlled by the standard Timer 0 control bits.
TH0 is an 8-bit timer only, controlled by Timer 1 control bits.
Rev. 0 | Page 60 of 88
There are no restrictions on the duty cycle of the external input
signal, but to ensure that a given level is sampled at least once
before it changes, it must be held for a minimum of one full
machine cycle. User configuration and control of all timer
operating modes is achieved via three SFRs:
TMOD, TCON
T2CON
TMOD
SFR Address
Power-On Default
Bit Addressable
Control and configuration for
Timers 0 and 1.
Control and configuration for
Timer 2.
Timer/Counter 0 and 1 Mode
Register
89H
00H
No