ADXL345BCCZ-RL Analog Devices Inc, ADXL345BCCZ-RL Datasheet - Page 32

• Manufacturer Part Number: ADXL345BCCZ-RL
• Description: Digital Output Three-Axis Accel 4K RL
• Manufacturer: Analog Devices Inc
• Series: iMEMS®r

Specifications of ADXL345BCCZ-RL

• Design Resources: Sensing Low-g Acceleration Using ADXL345 Digital Accelerometer Connected to ADuC7024 (CN0133)
• Axis: X, Y, Z
• Acceleration Range: ±2g, 4g, 8g, 16g
• Sensitivity: 256LSB/g, 128LSB/g, 64LSB/g, 32LSB/g
• Voltage - Supply: 2 V ~ 3.6 V
• Output Type: Digital
• Bandwidth: 6.25Hz ~ 3.2kHz Selectable
• Interface: I²C, SPI
• Mounting Type: Surface Mount
• Package / Case: 14-LGA
• Package Type: LGA
• Operating Supply Voltage (typ): 2.5V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Product Depth (mm): 3mm
• Product Length (mm): 5mm
• Mounting: Surface Mount
• Pin Count: 14
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADXL345BCCZ-RLTR

ADXL345
DATA FORMATTING OF UPPER DATA RATES
Formatting of output data at the 3200 Hz and 1600 Hz output
data rates changes depending on the mode of operation (full-
resolution or fixed 10-bit) and the selected output range.
When using the 3200 Hz or 1600 Hz output data rates in full-
resolution or ±2 g, 10-bit operation, the LSB of the output data-
word is always 0. When data is right justified, this corresponds
to Bit D0 of the DATAx0 register, as shown in Figure 48. When
data is left justified and the part is operating in ±2 g, 10-bit mode,
the LSB of the output data-word is Bit D6 of the DATAx0 register.
In full-resolution operation when data is left justified, the location
of the LSB changes according to the selected output range.
Figure 48. Data Formatting of Full-Resolution and ±2 g, 10-Bit Modes of Operation When Output Data Is Right Justified
Figure 49. Data Formatting of Full-Resolution and ±2 g, 10-Bit Modes of Operation When Output Data Is Left Justified
THE ±4g AND ±8g FULL-RESOLUTION MODES HAVE THE SAME LSB LOCATION AS THE ±2g
AND ±16g FULL-RESOLUTION MODES, BUT THE MSB LOCATION CHANGES TO BIT D2 AND
BIT D3 OF THE DATAX1 REGISTER FOR ±4g AND ±8g, RESPECTIVELY.
FOR 3200Hz AND 1600Hz OUTPUT DATA RATES, THE LSB IN THESE MODES IS ALWAYS 0.
ADDITIONALLY, ANY BITS TO THE RIGHT OF THE LSB ARE ALWAYS 0 WHEN THE OUTPUT
DATA IS LEFT JUSTIFIED.
DATAx1 REGISTER
OUTPUT DATA-WORD FOR
±16g, FULL-RESOLUTION MODE.
DATAx1 REGISTER
MSB FOR ALL MODES
OF OPERATION WHEN
LEFT JUSTIFIED.
D7
D7
D7
D7
D6
D6
D6
D6
D5
D5
D5
D5
D4
D4
D4
D4
LSB FOR ±2g, FULL-RESOLUTION
LSB FOR ±16g, FULL-RESOLUTION MODE.
LSB FOR ±4g, FULL-RESOLUTION MODE.
LSB FOR ±8g, FULL-RESOLUTION MODE.
D3
D3
D3
D3
D2
D2
D2
D2
AND ±2g, 10-BIT MODES.
D1
D1
D1
D1
Rev. B | Page 32 of 40
D0
D0
D0
D0
D7
D7
D7
D7
For a range of ±2 g, the LSB is Bit D6 of the DATAx0 register;
for ±4 g, Bit D5 of the DATAx0 register; for ±8 g, Bit D4 of the
DATAx0 register; and for ±16 g, Bit D3 of the DATAx0 register.
This is shown in Figure 49.
The use of 3200 Hz and 1600 Hz output data rates for fixed 10-
bit operation in the ±4 g, ±8 g, and ±16 g output ranges
provides an LSB that is valid and that changes according to the
applied acceleration. Therefore, in these modes of operation, Bit
D0 is not always 0 when output data is right justified and Bit D6
is not always 0 when output data is left justified. Operation at
any data rate of 800 Hz or lower also provides a valid LSB in all
ranges and modes that changes according to the applied
acceleration.
D6
D6
D6
D6
D5
D5
D5
D5
OUTPUT DATA-WORD FOR ALL
10-BIT MODES AND THE ±2g,
FULL-RESOLUTION MODE.
D4
D4
D4
D4
D3
D3
D3
D3
DATAx0 REGISTER
DATAx0 REGISTER
D2
D2
D2
D2
D1
D1
D1
D1
D0
D0
0
0