CS2000CP-CZZ Cirrus Logic Inc, CS2000CP-CZZ Datasheet
CS2000CP-CZZ
Specifications of CS2000CP-CZZ
CS2000CP-CZZ
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CS2000CP-CZZ Summary of contents
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Fractional-N Clock Synthesizer & Clock Multiplier Features Delta-Sigma Fractional-N Frequency Synthesis – Generates a Low Jitter MHz Clock from MHz Reference Clock Clock Multiplier / Jitter Reduction – Generates a Low ...
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TABLE OF CONTENTS 1. PIN DESCRIPTION ................................................................................................................................. 5 2. TYPICAL CONNECTION DIAGRAM ..................................................................................................... 6 3. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 7 RECOMMENDED OPERATING CONDITIONS .................................................................................... 7 ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 7 DC ELECTRICAL CHARACTERISTICS ................................................................................................ 7 AC ELECTRICAL CHARACTERISTICS ................................................................................................ 8 ...
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Auxiliary Output Source Selection (AuxOutSrc[1:0]) ............................................................. 29 8.3.4 Enable Device Configuration Registers 1 (EnDevCfg1) ........................................................ 30 8.4 Device Configuration 2 (Address 04h) ........................................................................................... 30 8.4.1 Lock Clock Ratio (LockClk[1:0]) ............................................................................................ 30 8.4.2 Fractional-N Source for Frequency Synthesizer (FracNSrc) ................................................. ...
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LIST OF TABLES Table 1. Ratio Modifier .............................................................................................................................. 20 Table 2. Example 12.20 R-Values ............................................................................................................ 34 Table 3. Example 20.12 R-Values ............................................................................................................ 34 4 CS2000-CP DS761F2 ...
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PIN DESCRIPTION VD GND CLK_OUT AUX_OUT CLK_IN Pin Name # Pin Description VD 1 Digital Power (Input) - Positive power supply for the digital and analog sections. GND 2 Ground (Input) - Ground reference. CLK_OUT 3 PLL Clock Output ...
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TYPICAL CONNECTION DIAGRAM 1 Note Notes: 1. Resistors 2 required for I C Ω operation. System MicroController Frequency Reference Low-Jitter Timing Reference Crystal 0.1 µF Ω SCL/CCLK SDA/CDIN AD0/CS ...
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CHARACTERISTICS AND SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS GND = 0 V; all voltages with respect to ground. Parameters DC Power Supply Ambient Operating Temperature (Power Applied) Notes: 1. Device functionality is not guaranteed or implied outside of these limits. Operation ...
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AC ELECTRICAL CHARACTERISTICS Test Conditions (unless otherwise specified 3 3 -40°C to +85°C (Automotive Grade Parameters Crystal Frequency Fundamental Mode XTAL Reference Clock Input Frequency Reference Clock Input Duty Cycle ...
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PLL PERFORMANCE PLOTS Test Conditions (unless otherwise specified 3 12.288 MHz; Sample size = 10,000 points; Base Band Jitter (100 kHz); AuxOutSrc[1:0] = 11. CLK_IN 10,000 1,000 100 10 1 0.1 ...
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CONTROL PORT SWITCHING CHARACTERISTICS- I²C FORMAT Inputs: Logic 0 = GND; Logic 1 = VD; C Parameter SCL Clock Frequency Bus Free-Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low Time Clock High Time Setup ...
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CONTROL PORT SWITCHING CHARACTERISTICS - SPI FORMAT Inputs: Logic 0 = GND; Logic 1 = VD; C Parameter CCLK Clock Frequency CCLK Edge to CS Falling CS High Time Between Transmissions CS Falling to CCLK Edge CCLK Low Time CCLK ...
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ARCHITECTURE OVERVIEW 4.1 Delta-Sigma Fractional-N Frequency Synthesizer The core of the CS2000 is a Delta-Sigma Fractional-N Frequency Synthesizer which has very high-resolu- tion for Input/Output clock ratios, low phase noise, very wide range of output frequencies and the ability ...
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Delta-Sigma Fractional-N Frequency Synthesizer Timing Reference Clock Digital PLL and Fractional-N Logic Frequency Reference Clock 4.2.1 Fractional-N Source Selection for the Frequency Synthesizer The fractional-N value for the frequency synthesizer can be sourced from either a static ratio or a ...
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APPLICATIONS 5.1 Timing Reference Clock Input The low jitter timing reference clock (RefClk) can be provided by either an external reference clock or an external crystal in conjunction with the internal oscillator. In order to maintain a stable and ...
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Crystal Connections (XTI and XTO) An external crystal may be used to generate RefClk. To accomplish this fundamental mode par- allel resonant crystal must be connected between the XTI and XTO pins as shown in nothing ...
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Regardless of the setting of the ClkSkipEn bit the PLL output will continue for 2 to 1048 ms) after CLK_IN is removed (see have an effective change in period as the clock source is removed, otherwise the PLL will interpret ...
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If CLK_IN is removed and then re-applied within t continues while the PLL re-acquires lock (see moved the PLL output will continue until CLK_IN is re-applied at which point the PLL will go unlocked only for the time it takes ...
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Typically, applications in which the PLL_OUT signal creates a new clock domain from which all other sys- tem clocks and associated data are derived will benefit from the maximum jitter and wander rejection of the lowest PLL bandwidth setting. See ...
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Output to Input Frequency Ratio Configuration 5.3.1 User Defined Ratio (R The User Defined Ratio, R desired input to output clock ratio four different ratios, Ratio space. The ratio pointed to by the RSel[1:0] bits is the ...
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Ratio Modifier (R-Mod) The Ratio Modifier is used to internally multiply/divide the currently addressed R the register space remain unchanged). The available options for R page 20. The R-Mod value selected by RModSel[2:0] is always used in the calculation ...
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Fractional-N Source Selection To select between the static ratio based Frequency Synthesizer Mode and the dynamic ratio based Hybrid PLL Mode, the source for the fractional-N value for the Frequency Synthesizer must be changed. The Fractional-N value can either ...
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Ratio Configuration Summary The R is the user defined ratio for which up to four different values (Ratio UD ister space. The RSel[1:0] or LockClk[1:0] bits then select the user defined ratio to be used (depending on if static ...
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PLL Clock Output The PLL clock output pin (CLK_OUT) provides a buffered version of the output of the frequency synthesizer. The driver can be set to high-impedance with the ClkOutDis bit. The output from the PLL automatically drives a ...
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Clock Output Stability Considerations 5.6.1 Output Switching CS2000 is designed such that re-configuration of the clock routing functions do not result in a partial clock period on any of the active outputs (CLK_OUT and/or AUX_OUT). In particular, enabling or ...
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The control port operates with either the SPI or I²C interface, with the CS2000 acting as a slave device. SPI Mode is selected if there is a high-to-low transition on the AD0/CS pin after power-up. I²C Mode is selected by ...
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SCL CHIP ADDRESS (WRITE AD0 0 SDA ACK START SCL CHIP ADDRESS (WRITE) SDA 1 0 ...
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Memory Address Pointer The Memory Address Pointer (MAP) byte comes after the address byte and selects the register to be read or written. Refer to the pseudocode above for implementation details. 6.3.1 Map Auto Increment The device has MAP ...
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REGISTER DESCRIPTIONS In I²C Mode all registers are read/write unless otherwise stated. In SPI mode all registers are write only. All “Re- served” registers must maintain their default state to ensure proper functional operation. The default state of each ...
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PLL Clock Output Disable (ClkOutDis) This bit controls the output driver for the CLK_OUT pin. ClkOutDis Output Driver State 0 CLK_OUT output driver enabled. 1 CLK_OUT output driver set to high-impedance. Application: “PLL Clock Output” on page 23 8.3 ...
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Enable Device Configuration Registers 1 (EnDevCfg1) This bit, in conjunction with EnDevCfg2, configures the device for control port mode. These EnDevCfg bits can be set in any order and at any time during the control port access sequence, however ...
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Enable Device Configuration Registers 2 (EnDevCfg2) This bit, in conjunction with EnDevCfg1, configures the device for control port mode. These EnDevCfg bits can be set in any order and at any time during the control port access sequence, however ...
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AUX PLL Lock Output Configuration (AuxLockCfg) When the AUX_OUT pin is configured as a lock indicator (AuxOutSrc[1:0] = 11), this bit configures the AUX_OUT driver to either push-pull or open drain. It also determines the polarity of the lock ...
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Function Configuration 3 (Address 1Eh Reserved ClkIn_BW2 ClkIn_BW1 8.9.1 Clock Input Bandwidth (ClkIn_BW[2:0]) Sets the minimum loop bandwidth when locked to CLK_IN. ClkIn_BW[2:0] Minimum Loop Bandwidth 000 1 Hz 001 2 Hz 010 4 Hz 011 8 ...
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CALCULATING THE USER DEFINED RATIO Note: The software for use with the evaluation kit has built in tools to aid in calculating and converting the User Defined Ratio. This section is for those who are not interested in the ...
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DIMENSIONS 10L MSOP (3 mm BODY) PACKAGE DRAWING TOP VIEW INCHES DIM MIN 0.0295 b 0.0059 c 0.0031 D -- 0.1181 BSC E -- 0.1929 BSC E1 -- 0.1181 ...
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... Changes “AC Electrical Characteristics” on page 2. “CLK_IN Skipping Mode” section on page 15 16. CS2000-CP Order# -10° to +70°C Rail CS2000CP-CZZ Tape and -10° to +70°C CS2000CP-CZZR Reel -40° to +85°C Rail CS2000CP-DZZ Tape and -40° to +85°C CS2000CP-DZZR Reel - - CDK2000-CLK 8. “AC Electrical Characteristics” on page ...
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DS761F2 CS2000-CP 37 ...
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Contacting Cirrus Logic Support For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find one nearest you www.cirrus.com IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this ...