CS2000CP-DZZR Cirrus Logic Inc, CS2000CP-DZZR Datasheet
CS2000CP-DZZR
Specifications of CS2000CP-DZZR
CS2000CP-DZZR
Related parts for CS2000CP-DZZR
CS2000CP-DZZR Summary of contents
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Fractional-N Clock Synthesizer & Clock Multiplier Features Delta-Sigma Fractional-N Frequency Synthesis – Generates a Low Jitter MHz Clock from MHz Reference Clock Clock Multiplier / Jitter Reduction – Generates a Low Jitter 6 ...
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TABLE OF CONTENTS 1. PIN DESCRIPTION ................................................................................................................................. 5 2. TYPICAL CONNECTION DIAGRAM ..................................................................................................... 6 3. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 7 RECOMMENDED OPERATING CONDITIONS .................................................................................... 7 ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 7 DC ELECTRICAL CHARACTERISTICS ................................................................................................ 7 AC ELECTRICAL CHARACTERISTICS ................................................................................................ 8 ...
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Ratio Selection (RSel[1:0]) .................................................................................................... 28 8.3.3 Auxiliary Output Source Selection (AuxOutSrc[1:0]) ............................................................. 29 8.3.4 Enable Device Configuration Registers 1 (EnDevCfg1) ........................................................ 29 8.4 Device Configuration 2 (Address 04h) ........................................................................................... 29 8.4.1 Auto R-Modifier Enable (AutoRMod) ..................................................................................... 29 8.4.2 Lock ...
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LIST OF TABLES Table 1. PLL Input Clock Range Indicator ................................................................................................ 14 Table 2. Ratio Modifier .............................................................................................................................. 18 Table 3. Automatic Ratio Modifier ............................................................................................................. 18 Table 4. Example Audio Oversampling Clock Generation from CLK_IN .................................................. 19 Table 5. Example 12.20 ...
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PIN DESCRIPTION VD GND CLK_OUT AUX_OUT CLK_IN Pin Name # Pin Description VD 1 Digital Power (Input) - Positive power supply for the digital and analog sections. GND 2 Ground (Input) - Ground reference. CLK_OUT 3 PLL Clock Output ...
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TYPICAL CONNECTION DIAGRAM 1 Note Notes: 1. Resistors 2 required for I C Ω operation. System MicroController Frequency Reference Low-Jitter Timing Reference Crystal 0.1 µF Ω SCL/CCLK SDA/CDIN AD0/CS ...
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CHARACTERISTICS AND SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS GND = 0 V; all voltages with respect to ground. Parameters DC Power Supply Ambient Operating Temperature (Power Applied) Notes: 1. Device functional operation is guaranteed within these limits. Functionality is not guaranteed ...
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AC ELECTRICAL CHARACTERISTICS Test Conditions (unless otherwise specified 3 3 pF. L Parameters Crystal Frequency Reference Clock Input Frequency Reference Clock Input Duty Cycle Internal System Clock Frequency Clock Input Frequency ...
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CONTROL PORT SWITCHING CHARACTERISTICS- I²C FORMAT Inputs: Logic 0 = GND; Logic 1 = VD; C Parameter SCL Clock Frequency Bus Free-Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low Time Clock High Time Setup ...
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CONTROL PORT SWITCHING CHARACTERISTICS - SPI FORMAT Inputs: Logic 0 = GND; Logic 1 = VD; C Parameter CCLK Clock Frequency CCLK Edge to CS Falling CS High Time Between Transmissions CS Falling to CCLK Edge CCLK Low Time CCLK ...
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ARCHITECTURE OVERVIEW 4.1 Delta-Sigma Fractional-N Frequency Synthesizer The core of the CS2000 is a Delta-Sigma Fractional-N Frequency Synthesizer which has very high-resolu- tion for Input/Output clock ratios, low phase noise, very wide range of output frequencies and the ability ...
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Delta-Sigma Fractional-N Frequency Synthesizer Timing Reference Clock Digital PLL and Fractional-N Logic Frequency Reference Clock 4.2.1 Fractional-N Source Selection for the Frequency Synthesizer The fractional-N value for the frequency synthesizer can be sourced from either a static ratio or a ...
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APPLICATIONS 5.1 Timing Reference Clock Input The low jitter timing reference clock (RefClk) can be provided by either an external reference clock or an external crystal in conjunction with the internal oscillator. In order to maintain a stable and ...
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External Reference Clock (REF_CLK) For operation with an externally generated REF_CLK signal, XTI/REF_CLK should be connected to the reference clock source and XTO should be left unconnected or pulled low through a 47 kΩ resistor to GND. 5.2 Frequency ...
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Electrical Characteristics” on page 8 output will resume. CLK_IN ClkSkipEn PLL_OUT ClkOutUnl=0 UNLOCK If CLK_IN is removed and then reapplied within 2 have no effect and the PLL output will continue until CLK_IN ...
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Adjusting the Minimum Loop Bandwidth for CLK_IN The CS2000 allows the minimum loop bandwidth of the Digital PLL to be adjusted between 1 Hz and 128 Hz using the ClkIn_BW[2:0] bits. The minimum loop bandwidth of the Digital PLL ...
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Output to Input Frequency Ratio Configuration 5.3.1 User Defined Ratio (R The User Defined Ratio, R desired input to output clock ratio four different ratios, Ratio space. The ratio pointed to by the RSel[1:0] bits is the ...
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Manual Ratio Modifier (R-Mod) The manual Ratio Modifier is used to internally multiply/divide the currently addressed R stored in the register space remain unchanged). The available options for R Table 2 on page 18. The R-Mod value selected by ...
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Frequency Range Indicator would then reflect the frequency range of the audio sample rate 512 would then generate the audio oversampling clocks as shown in UD Inferred Audio Sample Rate FsDetect[1:0] when SysClk=12.288 ...
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Fractional-N Source Selection To select between the static ratio based Frequency Synthesizer Mode and the dynamic ratio based Hybrid PLL Mode, the source for the fractional-N value for the Frequency Synthesizer must be changed. The Fractional-N value can either ...
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Ratio Configuration Summary The R is the user defined ratio for which up to four different values (Ratio UD ister space. The RSel[1:0] or LockClk[1:0] bits then select the user defined ratio to be used (depending on if static ...
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PLL Clock Output The PLL clock output pin (CLK_OUT) provides a buffered version of the output of the frequency synthesizer. The driver can be set to high-impedance with the ClkOutDis bit. The output from the PLL automatically drives a ...
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Clock Output Stability Considerations 5.6.1 Output Switching CS2000 is designed such that re-configuration of the clock routing functions do not result in a partial clock period on any of the active outputs (CLK_OUT and/or AUX_OUT). In particular, enabling or ...
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SPI / I²C CONTROL PORT The control port is used to access the registers and allows the device to be configured for the desired operational modes and formats. The operation of the control port may be completely asynchronous with ...
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R/W bit. If the operation is a write, the next byte is the Memory Address Point- er (MAP) which selects the register to be read or written. If the operation is a read, ...
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Memory Address Pointer The Memory Address Pointer (MAP) byte comes after the address byte and selects the register to be read or written. Refer to the pseudocode above for implementation details. 6.3.1 Map Auto Increment The device has MAP ...
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REGISTER DESCRIPTIONS In I²C Mode all registers are read/write unless otherwise stated. In SPI mode all registers are write only. All “Re- served” registers must maintain their default state to ensure proper functional operation. The default state of each ...
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Auxiliary Output Disable (AuxOutDis) This bit controls the output driver for the AUX_OUT pin. AuxOutDis Output Driver State 0 AUX_OUT output driver enabled. 1 AUX_OUT output driver set to high-impedance. Application: “Auxiliary Output” on page 22 8.2.4 PLL Clock ...
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Auxiliary Output Source Selection (AuxOutSrc[1:0]) Selects the source of the AUX_OUT signal. AuxOutSrc[1:0] Auxiliary Output Source 00 RefClk. 01 CLK_IN. 10 CLK_OUT. 11 PLL Lock Status Indicator. Application: “Auxiliary Output” on page 22 Note: When set to 11, AuxLckCfg ...
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Fractional-N Source for Frequency Synthesizer (FracNSrc) Selects static or dynamic ratio mode when auto clock switching is disabled. FracNSrc Fractional-N Source Selection Static Ratio directly from Dynamic Ratio from Digital PLL for Hybrid PLL Mode Application: ...
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Function Configuration 1 (Address 16h ClkSkipEn AuxLockCfg Reserved 8.7.1 Clock Skip Enable (ClkSkipEn) This bit enables clock skipping mode for the PLL and allows the PLL to maintain lock even when the CLK_IN has missing pulses. ClkSkipEn ...
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Function Configuration 2 (Address 17h Reserved Reserved Reserved 8.8.1 Enable PLL Clock Output on Unlock (ClkOutUnl) Defines the state of the PLL output during the PLL unlock condition. ClkOutUnl Clock Output Enable Status 0 Clock outputs are ...
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CALCULATING THE USER DEFINED RATIO Note: The software for use with the evaluation kit has built in tools to aid in calculating and converting the User Defined Ratio. This section is for those who are not interested in the ...
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DIMENSIONS 10L MSOP (3 mm BODY) PACKAGE DRAWING TOP VIEW INCHES DIM MIN 0.0295 b 0.0059 c 0.0031 D -- 0.1181 BSC E -- 0.1929 BSC E1 -- 0.1181 ...
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INFORMATION Product Description CS2000-CP Clocking Device CS2000-CP Clocking Device CDK2000 Evaluation Platform 12.REFERENCES 1. Audio Engineering Society AES-12id-2006: “AES Information Document for digital audio measurements - Jitter performance specifications,” May 2007. 2. Philips Semiconductor, “The I²C-Bus Specification: Version 2,” ...
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CS2000-CP DS761PP1 ...