CS2000CP-DZZR Cirrus Logic Inc, CS2000CP-DZZR Datasheet - Page 30

• Manufacturer Part Number: CS2000CP-DZZR
• Description: IC General Purpose PLL Crystal
• Manufacturer: Cirrus Logic Inc
• Type: Fractional N Synthesizerr

Specifications of CS2000CP-DZZR

• Pll: Yes
• Input: Clock
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 2:2
• Differential - Input:output: No/No
• Frequency - Max: 75MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 3.1 V ~ 3.5 V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Frequency-max: 75MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1572 - KIT EVAL PROTOTYPING CS2300-CP598-1571 - KIT EVAL PROTOTYPING CS2000-CP598-1493 - BOARD EVAL GEN PURPOSE PLL DC598-1492 - BOARD EVAL GEN PURPOSE PLL DC598-1490 - BOARD EVAL GEN PURPOSE PLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 598-1400-2; CS2000CP-DZZR

30
8.4.3
8.5
8.5.1
8.5.2
8.6
Reserved
LSB+15
MSB-8
LSB+7
MSB
7
7
Global Configuration (Address 05h)
Ratio 0 - 3 (Address 06h - 15h)
These registers contain the User Defined Ratios as shown in the
page
Frequency Ratio Configuration” on page 17
details.
Fractional-N Source for Frequency Synthesizer (FracNSrc)
Selects static or dynamic ratio mode when auto clock switching is disabled.
Setting this bit allows writes to the Device Control and Device Configuration registers (address 02h - 04h)
but keeps them from taking effect until this bit is cleared.
Enable Device Configuration Registers 2 (EnDevCfg2)
This bit, in conjunction with EnDevCfg1, enables control port mode. Both bits must be set to 1 during ini-
tialization.
Note:
FracNSrc
0
1
Application:
FREEZE
0
1
EnDevCfg2
0
1
Application:
Device Configuration Freeze (Freeze)
26. Each group of 4 registers forms a single 32-bit ratio value as shown above. See
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Reserved
EnDevCfg1 must also be set to enable control port mode
6
6
Fractional-N Source Selection
Static Ratio directly from R
Dynamic Ratio from Digital PLL for Hybrid PLL Mode
“Fractional-N Source Selection” on page 20
Device Control and Configuration Registers
Register changes take effect immediately.
Modifications may be made to Device Control and Device Configuration registers (registers 02h-04h) without
the changes taking effect until after the FREEZE bit is cleared.
Register State
Disabled.
Enabled.
“SPI / I²C Control Port” on page 24
Reserved
5
5
Reserved
EFF
4
4
for Frequency Synthesizer Mode
and
“Calculating the User Defined Ratio” on page 33
Freeze
3
3
Reserved
“Register Quick Reference” section on
(“SPI / I²C Control Port” on page
2
2
Reserved
1
1
CS2000-CP
“Output to Input
EnDevCfg2
DS761PP1
MSB-15
MSB-7
LSB+8
LSB
for more
0
0
24).