CS2000CP-DZZR Cirrus Logic Inc, CS2000CP-DZZR Datasheet - Page 17

• Manufacturer Part Number: CS2000CP-DZZR
• Description: IC General Purpose PLL Crystal
• Manufacturer: Cirrus Logic Inc
• Type: Fractional N Synthesizerr

Specifications of CS2000CP-DZZR

• Pll: Yes
• Input: Clock
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 2:2
• Differential - Input:output: No/No
• Frequency - Max: 75MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 3.1 V ~ 3.5 V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Frequency-max: 75MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1572 - KIT EVAL PROTOTYPING CS2300-CP598-1571 - KIT EVAL PROTOTYPING CS2000-CP598-1493 - BOARD EVAL GEN PURPOSE PLL DC598-1492 - BOARD EVAL GEN PURPOSE PLL DC598-1490 - BOARD EVAL GEN PURPOSE PLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 598-1400-2; CS2000CP-DZZR

DS761PP1
5.3
5.3.1
5.3.2
Output to Input Frequency Ratio Configuration
User Defined Ratio (R
The User Defined Ratio, R
desired input to output clock ratio. Up to four different ratios, Ratio
space. The ratio pointed to by the RSel[1:0] bits is the currently selected ratio for the static ratio based
Frequency Synthesizer Mode. The 32-bit R
12 MSBs represent the integer binary portion while the remaining 20 LSBs represent the fractional binary
portion. The maximum multiplication factor is approximately 4096 with a resolution of 0.954 PPM in this
configuration. See
The status of internal dividers, such as the internal timing reference clock divider, are automatically taken
into account. Therefore R
User Defined Ratio (R
The same four ratio locations, Ratio
The User Defined Ratio pointed to by the LockClk[1:0] bits is the currently selected ratio for the dynamic
ratio based Hybrid PLL Mode.
In addition to the High-Resolution format, a High-Multiplication format is also available. In the High-Multi-
plication Format Mode, the 32-bit R
integer binary portion while the remaining 12 LSBs represent the fractional binary portion. In this config-
uration, the maximum multiplication factor is approximately 1,048,575 with a resolution of 244 PPM.
The ratio format default is 20.12. The 20.12 ratio format is only available when both the LFRatioCfg bit is
cleared (20.12) and the FracNSrc bit is set (dynamic ratio). In Auto Fractional-N Source Mode (see
5.3.6.2 on page
12.20.
It is recommended that the 12.20 High-Resolution format be utilized whenever the desired ratio is less
than 4096 since the output frequency accuracy of the PLL is directly proportional to the accuracy of the
timing reference clock and the resolution of the R
Referenced Control
Ratio 0-3
Rsel[1:0]
Referenced Control
LockClk[1:0]
LFRatioCfg
FracNSrc
.................................“Ratio 0 - 3 (Address 06h - 15h)” on page 30
................................“Ratio Selection (RSel[1:0])” on page 28
...............................“Fractional-N Source for Frequency Synthesizer (FracNSrc)” section on page 30
............................“Low-Frequency Ratio Configuration (LFRatioCfg)” on page 32
..........................“Lock Clock Ratio (LockClk[1:0])” section on page 29
20) when CLK_IN is not present the LFRatioCfg bit is ignored and the ratio format is
“Calculating the User Defined Ratio” on page 33
Register Location
Register Location
UD
UD
UD
UD
, is a 32-bit un-signed fixed-point number which determines the basis for the
is simply the desired ratio of the output to input clock frequencies.
), Frequency Synthesizer Mode
), Hybrid PLL Mode
UD
0-3
is represented in a 20.12 format where the 20 MSBs represent the
, are used to store the User Defined Ratios for Hybrid PLL Mode.
UD
is represented in a high-resolution 12.20 format where the
UD
.
0-3
, can be stored in the CS2000 register
for more information.
CS2000-CP
section
17