CS2000CP-DZZR Cirrus Logic Inc, CS2000CP-DZZR Datasheet - Page 15

• Manufacturer Part Number: CS2000CP-DZZR
• Description: IC General Purpose PLL Crystal
• Manufacturer: Cirrus Logic Inc
• Type: Fractional N Synthesizerr

Specifications of CS2000CP-DZZR

• Pll: Yes
• Input: Clock
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 2:2
• Differential - Input:output: No/No
• Frequency - Max: 75MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 3.1 V ~ 3.5 V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Frequency-max: 75MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1572 - KIT EVAL PROTOTYPING CS2300-CP598-1571 - KIT EVAL PROTOTYPING CS2000-CP598-1493 - BOARD EVAL GEN PURPOSE PLL DC598-1492 - BOARD EVAL GEN PURPOSE PLL DC598-1490 - BOARD EVAL GEN PURPOSE PLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 598-1400-2; CS2000CP-DZZR

DS761PP1
ClkSkipEn=0 or 1
ClkOutUnl=0
time listed in the
output will resume.
If CLK_IN is removed and then reapplied within 2
have no effect and the PLL output will continue until CLK_IN is re-applied (see
is re-applied, the PLL will go unlocked only for the time it takes to acquire lock; the PLL_OUT state will be
determined by the ClkOutUnl bit during this time.
If CLK_IN is removed and then re-applied within t
continues while the PLL re-acquires lock (see
moved the PLL output will continue until CLK_IN is re-applied at which point the PLL will go unlocked only
for the time it takes to acquire lock; the PLL_OUT state will be determined by the ClkOutUnl bit during this
time. When ClkSkipEn is enabled and CLK_IN is removed the PLL output clock will remain continuous
throughout the missing CLK_IN period including the time while the PLL re-acquires lock.
ClkSkipEn=1
ClkOutUnl=0 or 1
Referenced Control
ClkSkipEn..............................“Clock Skip Enable (ClkSkipEn)” on page 31
ClkOutUnl..............................“Enable PLL Clock Output on Unlock (ClkOutUnl)” on page 32
ClkSkipEn=0 or 1
ClkOutUnl=0
PLL_OUT
UNLOCK
PLL_OUT
UNLOCK
CLK_IN
PLL_OUT
CLK_IN
UNLOCK
CLK_IN
“AC Electrical Characteristics” on page 8
Figure 10. CLK_IN removed for < 2
Register Location
Figure 9. CLK_IN removed for > 2
t
CS
ClkSkipEn=0
ClkOutUnl=0
2
23
Lock Time
Figure 11. CLK_IN removed for < t
SysClk cycles
PLL_OUT
UNLOCK
CLK_IN
2
23
Lock Time
SysClk cycles
t
CS
Figure
23
CS
SysClk cycles but later than t
ClkSkipEn=0 or 1
ClkOutUnl=1
11). When ClkSkipEn is disabled and CLK_IN is re-
, the ClkSkipEn bit determines whether PLL_OUT
ClkSkipEn=0 or 1
ClkOutUnl=1
23
ClkSkipEn=0
ClkOutUnl=1
Lock Time
after which lock will be acquired and the PLL
SysClk cycles but > t
23
SysClk cycles
PLL_OUT
UNLOCK
CLK_IN
PLL_OUT
PLL_OUT
UNLOCK
UNLOCK
t
CLK_IN
CS
CLK_IN
CS
Figure
t
CS
CS
= invalid clocks
CS
= invalid clocks
, the ClkSkipEn bit will
= invalid clocks
2
Lock Time
23
10). Once CLK_IN
SysClk cycles
Lock Time
CS2000-CP
2
23
Lock Time
SysClk cycles
t
CS
15