CS2000CP-DZZR Cirrus Logic Inc, CS2000CP-DZZR Datasheet - Page 26

• Manufacturer Part Number: CS2000CP-DZZR
• Description: IC General Purpose PLL Crystal
• Manufacturer: Cirrus Logic Inc
• Type: Fractional N Synthesizerr

Specifications of CS2000CP-DZZR

• Pll: Yes
• Input: Clock
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 2:2
• Differential - Input:output: No/No
• Frequency - Max: 75MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 3.1 V ~ 3.5 V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Frequency-max: 75MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1572 - KIT EVAL PROTOTYPING CS2300-CP598-1571 - KIT EVAL PROTOTYPING CS2000-CP598-1493 - BOARD EVAL GEN PURPOSE PLL DC598-1492 - BOARD EVAL GEN PURPOSE PLL DC598-1490 - BOARD EVAL GEN PURPOSE PLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 598-1400-2; CS2000CP-DZZR

26
6.3
6.3.1
7. REGISTER QUICK REFERENCE
This table shows the register and bit names with their associated default values.
EnDevCfg1 and EnDevCfg2 bits must be set to 1 for normal operation.
WARNING: All “Reserved” registers must maintain their default state to ensure proper functional operation.
Adr
p 27
p 27
p 28
p 29
p 30
p 31
p 32
p 32
0Ah
0Dh
0Eh
1Eh
01h
02h
03h
04h
05h
06h
09h
11h
12h
15h
16h
17h
-
-
-
-
Device ID
Device Ctrl
Device Cfg 1
Device Cfg 2
Global Cfg
32-Bit
Ratio 0
32-Bit
Ratio 1
32-Bit
Ratio 2
32-Bit
Ratio 3
Funct Cfg 1
Funct Cfg 2
Funct Cfg 3
Memory Address Pointer
The Memory Address Pointer (MAP) byte comes after the address byte and selects the register to be read
or written. Refer to the pseudocode above for implementation details.
Name
Map Auto Increment
The device has MAP auto increment capability enabled by the INCR bit (the MSB) of the MAP. If INCR is
set to 0, MAP will stay constant for successive I²C writes or reads and SPI writes. If INCR is set to 1, MAP
will auto increment after each byte is read or written, allowing block reads or writes of successive regis-
ters.
RModSel2
ClkSkipEn AuxLockCfg
Reserved
Reserved
Reserved
Reserved
Device4
LSB+15
LSB+15
LSB+15
LSB+15
Unlock
MSB-8
LSB+7
MSB-8
LSB+7
MSB-8
LSB+7
MSB-8
LSB+7
MSB
MSB
MSB
MSB
7
0
x
0
0
0
0
0
0
ClkIn_BW2 ClkIn_BW1 ClkIn_BW0
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RModSel1
Reserved
Reserved
Reserved
Device3
FsDet1
6
0
0
0
0
0
0
0
x
RModSel0
Reserved
Reserved
Reserved
Reserved
Device2
FsDet0
5
0
0
0
0
0
0
0
x
RefClkDiv1 RefClkDiv0
ClkOutUnl
Reserved
Reserved
Reserved
Device1
RSel1
4
0
0
0
0
0
0
0
0
LFRatioCfg
AutoRMod
Reserved
Reserved
Device0
Freeze
RSel0
3
0
0
0
0
0
0
0
0
AuxOutSrc1 AuxOutSrc0 EnDevCfg1
Revision2
Reserved
Reserved
Reserved
Reserved
Reserved
LockClk1
2
0
0
0
0
0
0
0
x
AuxOutDis
Revision1
Reserved
Reserved
Reserved
Reserved
LockClk0
1
0
0
0
0
0
0
0
x
CS2000-CP
DS761PP1
EnDevCfg2
ClkOutDis
Revision0
Reserved
FracNSrc
Reserved
Reserved
MSB-15
MSB-15
MSB-15
MSB-15
MSB-7
LSB+8
MSB-7
LSB+8
MSB-7
LSB+8
MSB-7
LSB+8
LSB
LSB
LSB
LSB
0
0
0
0
0
0
0
0
x