CS2000CP-DZZR Cirrus Logic Inc, CS2000CP-DZZR Datasheet - Page 21

• Manufacturer Part Number: CS2000CP-DZZR
• Description: IC General Purpose PLL Crystal
• Manufacturer: Cirrus Logic Inc
• Type: Fractional N Synthesizerr

Specifications of CS2000CP-DZZR

• Pll: Yes
• Input: Clock
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 2:2
• Differential - Input:output: No/No
• Frequency - Max: 75MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 3.1 V ~ 3.5 V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Frequency-max: 75MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1572 - KIT EVAL PROTOTYPING CS2300-CP598-1571 - KIT EVAL PROTOTYPING CS2000-CP598-1493 - BOARD EVAL GEN PURPOSE PLL DC598-1492 - BOARD EVAL GEN PURPOSE PLL DC598-1490 - BOARD EVAL GEN PURPOSE PLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 598-1400-2; CS2000CP-DZZR

DS761PP1
5.3.7
User Defined Ratio R
Ratio 0
Ratio 1
Ratio 2
Ratio 3
Ratio Configuration Summary
The R
ister space. The RSel[1:0] or LockClk[1:0] bits then select the user defined ratio to be used (depending
on if static or dynamic ratio mode is to be used). The resolution for the R
ratio mode, by setting LFRatioCfg. R-Mods can be applied to both modes whereas Auto R-Mod is only
available in dynamic mode. The user defined ratio, ratio modifier, and automatic ratio modifier make up
the effective ratio R
ratio is then corrected for the internal dividers. The frequency synthesizer’s fractional-N source selection
is made between the static ratio (in frequency synthesizer mode) or the dynamic ratio generated from the
digital PLL (in Hybrid PLL mode) by either the FracNSrc bit for manual mode or the presence of CLK_IN
in automatic mode. The conceptual diagram in
lation of the ratio values used to generate the fractional-N value which controls the Frequency Synthesiz-
er.
Referenced Control
Ratio 0-3
RSel[1:0]
LockClk[1:0]
LFRatioCfg
RModSel[2:0]
AutoRMod
FsDet[1:0]..............................“PLL Input Sample Rate Indicator (FsDet[1:0]) - Read Only” section on page 27
RefClkDiv[1:0]
FracNSrc
UD
LockClk[1:0]
RSel[1:0]
UD
.................................“Ratio 0 - 3 (Address 06h - 15h)” on page 30
...............................“Ratio Selection (RSel[1:0])” on page 28
...............................“Fractional-N Source for Frequency Synthesizer (FracNSrc)” section on page 30
Effective Ratio R
is the user defined ratio for which up to four different values (Ratio
.............................“Auto R-Modifier Enable (AutoRMod)” on page 29
............................“Low-Frequency Ratio Configuration (LFRatioCfg)” on page 32
..........................“Lock Clock Ratio (LockClk[1:0])” section on page 29
........................“R-Mod Selection (RModSel[2:0])” section on page 28
Ratio Format
.......................“Reference Clock Input Divider (RefClkDiv[1:0])” on page 31
LFRatioCfg
12.20
12.20
20.12
only
EFF
EFF
RModSel[2:0]
, the final calculation used to determine the output to input clock ratio. The effective
Register Location
Modifier
Modifier
Ratio
Ratio
AutoRMod
Figure 14. Ratio Feature Summary
FsDet[1:0]
R-Mod
Auto
RefClkDiv[1:0]
R Correction
R Correction
(manual selection)
(auto selection)
CLK_IN sense
Figure 14
Frequency Reference Clock
FracNSrc
Fractional N Logic
Dynamic Ratio
Digital PLL &
RSel[1:0] =? LockClk[1:0]
Static Ratio
(CLK_IN)
≠
=
summarizes the features involved in the calcu-
CLK_IN not present
or FracNSrc=0
CLK_IN present
or FracNSrc=1
N
Timing Reference Clock
(XTI/REF_CLK)
Divide
SysClk
UD
is selectable, for the dynamic
0-3
) can be stored in the reg-
RefClkDiv[1:0]
Synthesizer
Frequency
CS2000-CP
PLL Output
21