CS2000CP-DZZR Cirrus Logic Inc, CS2000CP-DZZR Datasheet - Page 8

• Manufacturer Part Number: CS2000CP-DZZR
• Description: IC General Purpose PLL Crystal
• Manufacturer: Cirrus Logic Inc
• Type: Fractional N Synthesizerr

Specifications of CS2000CP-DZZR

• Pll: Yes
• Input: Clock
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 2:2
• Differential - Input:output: No/No
• Frequency - Max: 75MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 3.1 V ~ 3.5 V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Frequency-max: 75MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1572 - KIT EVAL PROTOTYPING CS2300-CP598-1571 - KIT EVAL PROTOTYPING CS2000-CP598-1493 - BOARD EVAL GEN PURPOSE PLL DC598-1492 - BOARD EVAL GEN PURPOSE PLL DC598-1490 - BOARD EVAL GEN PURPOSE PLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 598-1400-2; CS2000CP-DZZR

8
AC ELECTRICAL CHARACTERISTICS
Test Conditions (unless otherwise specified): VD = 3.1 V to 3.5 V; T
C
Notes: 3. 1 UI (unit interval) corresponds to t
Crystal Frequency
Reference Clock Input Frequency
Reference Clock Input Duty Cycle
Internal System Clock Frequency
Clock Input Frequency (Auto R-Mod Disabled)
Clock Input Frequency (Auto R-mod Enabled)
Clock Input Pulse Width
Clock Skipping Timeout
Clock Skipping Input Frequency
PLL Clock Output Frequency
PLL Clock Output Duty Cycle
Clock Output Rise Time
Clock Output Fall Time
Period Jitter
Base Band Jitter (100 Hz to 40 kHz)
Wide Band JItter (100 Hz Corner)
PLL Lock Time - CLK_IN
PLL Lock Time - REF_CLK
Output Frequency Synthesis Resolution
L
= 15 pF.
4. t
5. Only valid in clock skipping mode; See
6.
7. In accordance with AES-12id-2006 section 3.4.2. Measurements are Time Interval Error taken with 3rd
8. In accordance with AES-12id-2006 section 3.4.1. Measurements are Time Interval Error taken with 3rd
9. 1 UI (unit interval) corresponds to t
10. The frequency accuracy of the PLL clock output is directly proportional to the frequency accuracy of the
PLL_OUT continues while the PLL re-acquires lock. This timeout is based on the internal VCO frequen-
cy, with the minimum timeout occurring at the maximum VCO frequency. Lower VCO frequencies will
result in larger values of t
f
order 100 Hz to 40 kHz bandpass filter.
order 100 Hz Highpass filter.
reference clock.
CS
CLK_OUT
represents the time from the removal of CLK_IN by which CLK_IN must be re-applied to ensure that
Parameters
= 24.576 MHz; Sample size = 10,000 points; AuxOutSrc[1:0] = 11.
(Note
(Note
3)
9)
(Note
CS
.
10)
D
SYS_CLK
CLK_IN
f
Symbol
pw
f
f
f
CLK_SKIP
REF_CLK
SYS_CLK
CLK_OUT
f
f
REF_CLK
CLK_IN
CLK_IN
f
XTAL
CLK_IN
t
t
t
t
t
t
t
f
OD
OR
CS
OF
JIT
LC
LR
err
“CLK_IN Skipping Mode” on page 14
or 1/f
or 1/f
f
CLK_IN
Auto R Modifier = 0.25
REF_CLK
f
f
Auto R Modifier = 0.5
CLK_IN
CLK_IN
Fundamental Mode
Auto R Modifier = 1
20% to 80% of VD
80% to 20% of VD
SYS_CLK
Measured at VD/2
High Multiplication
f
f
CLK_IN
CLK_IN
High Resolution
Conditions
(Notes 4, 5)
(Notes 6, 7)
(Notes 6, 8)
.
(Note
(Note
< f
> f
= 8 to 75 MHz
A
< 200 kHz
> 200 kHz
SYS_CLK
SYS_CLK
.
= -10°C to +70°C (Commercial Grade);
5)
6)
/96
/96
50 Hz
50 Hz
Min
168
45
72
10
20
48
8
8
8
4
2
6
0
0
-
-
-
-
-
-
-
-
for more information.
Typ
175
100
1.7
1.7
50
70
50
1
1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
CS2000-CP
18.75
Max
±112
±0.5
138
256
150
200
3.0
3.0
50
75
55
30
59
80
75
52
3
2
-
-
-
-
-
DS761PP1
ps rms
ps rms
ps rms
Units
MHz
MHz
MHz
MHz
MHz
ppm
ppm
kHz
kHz
kHz
kHz
ms
ms
ms
ns
ns
ns
%
UI
%
UI