CS2000CP-DZZR Cirrus Logic Inc, CS2000CP-DZZR Datasheet - Page 13

• Manufacturer Part Number: CS2000CP-DZZR
• Description: IC General Purpose PLL Crystal
• Manufacturer: Cirrus Logic Inc
• Type: Fractional N Synthesizerr

Specifications of CS2000CP-DZZR

• Pll: Yes
• Input: Clock
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 2:2
• Differential - Input:output: No/No
• Frequency - Max: 75MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 3.1 V ~ 3.5 V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Frequency-max: 75MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1572 - KIT EVAL PROTOTYPING CS2300-CP598-1571 - KIT EVAL PROTOTYPING CS2000-CP598-1493 - BOARD EVAL GEN PURPOSE PLL DC598-1492 - BOARD EVAL GEN PURPOSE PLL DC598-1490 - BOARD EVAL GEN PURPOSE PLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 598-1400-2; CS2000CP-DZZR

DS761PP1
5. APPLICATIONS
5.1
5.1.1
5.1.2
Timing Reference Clock Input
The low jitter timing reference clock (RefClk) can be provided by either an external reference clock or an
external crystal in conjunction with the internal oscillator. In order to maintain a stable and low-jitter PLL out-
put the timing reference clock must also be stable and low-jitter; the quality of the timing reference clock
directly affects the performance of the PLL and hence the quality of the PLL output.
Internal Timing Reference Clock Divider
The Internal Timing Reference Clock (SysClk) has a smaller maximum frequency than what is allowed on
the XTI/REF_CLK pin. The CS2000 supports the wider external frequency range by offering an internal
divider for RefClk. The RefClkDiv[1:0] bits should be set such that SysClk, the divided RefClk, then falls
within the valid range as indicated in
It should be noted that the maximum allowable input frequency of the XTI/REF_CLK pin is dependent
upon its configuration as either a crystal connection or external clock input. See the
acteristics” on page 8
Crystal Connections (XTI and XTO)
An external crystal may be used to generate RefClk. To accomplish this, a 20 pF fundamental mode par-
allel resonant crystal must be connected between the XTI and XTO pins as shown in
nothing other than the crystal and its load capacitors should be connected to XTI and XTO. Please refer
to the
XTI/REF_CLK
Referenced Control
RefClkDiv[1:0]
“AC Electrical Characteristics” on page 8
.......................“Reference Clock Input Divider (RefClkDiv[1:0])” on page 31
8 MHz < RefClk <
Figure 8. External Component Requirements for Crystal Circuit
Timing Reference Clock
Figure 7. Internal Timing Reference Clock Divider
for more details.
Register Location
50 MHz (XTI)
75 MHz (REF_CLK)
40 pF
XTI
Figure
Timing Reference
Clock Divider
RefClkDiv[1:0]
÷
÷
÷
7.
1
2
4
for the allowed crystal frequency range.
XTO
8 MHz < SysClk < 18.75 MHz
40 pF
Reference Clock
Internal Timing
Synthesizer
Frequency
Fractional-N
N
“AC Electrical Char-
Figure
CS2000-CP
8. As shown,
PLL Output
13