CS2000CP-DZZR Cirrus Logic Inc, CS2000CP-DZZR Datasheet - Page 24

• Manufacturer Part Number: CS2000CP-DZZR
• Description: IC General Purpose PLL Crystal
• Manufacturer: Cirrus Logic Inc
• Type: Fractional N Synthesizerr

Specifications of CS2000CP-DZZR

• Pll: Yes
• Input: Clock
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 2:2
• Differential - Input:output: No/No
• Frequency - Max: 75MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 3.1 V ~ 3.5 V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Frequency-max: 75MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1572 - KIT EVAL PROTOTYPING CS2300-CP598-1571 - KIT EVAL PROTOTYPING CS2000-CP598-1493 - BOARD EVAL GEN PURPOSE PLL DC598-1492 - BOARD EVAL GEN PURPOSE PLL DC598-1490 - BOARD EVAL GEN PURPOSE PLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 598-1400-2; CS2000CP-DZZR

24
6. SPI / I²C CONTROL PORT
The control port is used to access the registers and allows the device to be configured for the desired operational
modes and formats. The operation of the control port may be completely asynchronous with respect to device inputs
and outputs. However, to avoid potential interference problems, the control port pins should remain static if no op-
eration is required.
The control port operates with either the SPI or I²C interface, with the CS2000 acting as a slave device. SPI Mode
is selected if there is a high-to-low transition on the AD0/CS pin after power-up. I²C Mode is selected by connecting
the AD0/CS pin through a resistor to VD or GND, thereby permanently selecting the desired AD0 bit address state.
In both modes the EnDevCfg1 and EnDevCfg2 bits must be set to 1 for normal operation.
6.1
6.2
WARNING: All “Reserved” registers must maintain their default state to ensure proper functional operation.
Referenced Control
EnDevCfg1
EnDevCfg2
SPI Control
In SPI Mode, CS is the chip select signal; CCLK is the control port bit clock (sourced from a microcontroller),
and CDIN is the input data line from the microcontroller. Data is clocked in on the rising edge of CCLK. The
device only supports write operations.
Figure 17
eight bits on CDIN form the chip address and must be 10011110. The next eight bits form the Memory Ad-
dress Pointer (MAP), which is set to the address of the register that is to be updated. The next eight bits are
the data which will be placed into the register designated by the MAP.
There is MAP auto increment capability, enabled by the INCR bit in the MAP register. If INCR is a zero, the
MAP will stay constant for successive read or writes. If INCR is set to a 1, the MAP will automatically incre-
ment after each byte is read or written, allowing block writes of successive registers.
CCLK
I²C Control
In I²C Mode, SDA is a bidirectional data line. Data is clocked into and out of the device by the clock, SCL.
There is no CS pin. The AD0 pin forms the least-significant bit of the chip address and should be connected
to VD or GND as appropriate. The state of the AD0 pin should be maintained throughout operation of the
device.
The signal timings for a read and write cycle are shown in
fined as a falling transition of SDA while the clock is high. A Stop condition is a rising transition while the
clock is high. All other transitions of SDA occur while the clock is low. The first byte sent to the
a Start condition consists of the 7-bit chip address field and a R/W bit (high for a read, low for a write). The
upper 6 bits of the 7-bit address field are fixed at 100111 followed by the logic state of the AD0 pin. The
CDIN
............................“Enable Device Configuration Registers 1 (EnDevCfg1)” on page 29
............................“Enable Device Configuration Registers 2 (EnDevCfg2)” section on page 30
CS
shows the operation of the control port in SPI Mode. To write to a register, bring CS low. The first
0
1
1
Register Location
0
CHIP ADDRESS
2
0
3
1
4
1
5
1
Figure 17. Control Port Timing in SPI Mode
6
1
7
0
INCR
8
9
6
10 11
MAP BYTE
5
4
12
3
13 14 15
2
1
0
Figure 18
16 17
7
6
DATA
1
and
0
Figure
7
DATA +n
6
19. A Start condition is de-
1
0
CS2000-CP
CS2000
DS761PP1
after