CS2000CP-DZZR Cirrus Logic Inc, CS2000CP-DZZR Datasheet - Page 3

• Manufacturer Part Number: CS2000CP-DZZR
• Description: IC General Purpose PLL Crystal
• Manufacturer: Cirrus Logic Inc
• Type: Fractional N Synthesizerr

Specifications of CS2000CP-DZZR

• Pll: Yes
• Input: Clock
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 2:2
• Differential - Input:output: No/No
• Frequency - Max: 75MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 3.1 V ~ 3.5 V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Frequency-max: 75MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1572 - KIT EVAL PROTOTYPING CS2300-CP598-1571 - KIT EVAL PROTOTYPING CS2000-CP598-1493 - BOARD EVAL GEN PURPOSE PLL DC598-1492 - BOARD EVAL GEN PURPOSE PLL DC598-1490 - BOARD EVAL GEN PURPOSE PLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 598-1400-2; CS2000CP-DZZR

DS761PP1
LIST OF FIGURES
9. CALCULATING THE USER DEFINED RATIO .................................................................................... 33
10. PACKAGE DIMENSIONS .................................................................................................................. 34
11. ORDERING INFORMATION .............................................................................................................. 35
12. REFERENCES .................................................................................................................................... 35
13. REVISION HISTORY .......................................................................................................................... 35
Figure 1. Typical Connection Diagram ........................................................................................................ 6
Figure 2. Control Port Timing - I²C Format .................................................................................................. 9
Figure 3. Control Port Timing - SPI Format (Write Only) .......................................................................... 10
Figure 4. Delta-Sigma Fractional-N Frequency Synthesizer ..................................................................... 11
Figure 5. Hybrid Analog-Digital PLL .......................................................................................................... 12
Figure 6. Fractional-N Source Selection Overview ................................................................................... 12
Figure 7. Internal Timing Reference Clock Divider ................................................................................... 13
Figure 8. External Component Requirements for Crystal Circuit .............................................................. 13
Figure 9. CLK_IN removed for > 2
Figure 10. CLK_IN removed for < 2
Figure 11. CLK_IN removed for < t
Figure 12. Low bandwidth and new clock domain .................................................................................... 16
Figure 13. High bandwidth with CLK_IN domain re-use ........................................................................... 16
Figure 14. Ratio Feature Summary ........................................................................................................... 21
Figure 15. PLL Clock Output Options ....................................................................................................... 22
Figure 16. Auxiliary Output Selection ........................................................................................................ 22
Figure 17. Control Port Timing in SPI Mode ............................................................................................. 24
Figure 18. Control Port Timing, I²C Write .................................................................................................. 25
Figure 19. Control Port Timing, I²C Aborted Write + Read ....................................................................... 25
8.4 Device Configuration 2 (Address 04h) ........................................................................................... 29
8.5 Global Configuration (Address 05h) ............................................................................................... 30
8.6 Ratio 0 - 3 (Address 06h - 15h) ...................................................................................................... 30
8.7 Function Configuration 1 (Address 16h) ........................................................................................ 31
8.8 Function Configuration 2 (Address 17h) ........................................................................................ 32
8.9 Function Configuration 3 (Address 1Eh) ........................................................................................ 32
9.1 High Resolution 12.20 Format ....................................................................................................... 33
9.2 High Multiplication 20.12 Format ................................................................................................... 33
THERMAL CHARACTERISTICS ......................................................................................................... 34
8.3.2 Ratio Selection (RSel[1:0]) .................................................................................................... 28
8.3.3 Auxiliary Output Source Selection (AuxOutSrc[1:0]) ............................................................. 29
8.3.4 Enable Device Configuration Registers 1 (EnDevCfg1) ........................................................ 29
8.4.1 Auto R-Modifier Enable (AutoRMod) ..................................................................................... 29
8.4.2 Lock Clock Ratio (LockClk[1:0]) ............................................................................................ 29
8.4.3 Fractional-N Source for Frequency Synthesizer (FracNSrc) ................................................. 30
8.5.1 Device Configuration Freeze (Freeze) ................................................................................ 30
8.5.2 Enable Device Configuration Registers 2 (EnDevCfg2) ....................................................... 30
8.7.1 Clock Skip Enable (ClkSkipEn) ............................................................................................. 31
8.7.2 AUX PLL Lock Output Configuration (AuxLockCfg) .............................................................. 31
8.7.3 Reference Clock Input Divider (RefClkDiv[1:0]) .................................................................... 31
8.8.1 Enable PLL Clock Output on Unlock (ClkOutUnl) ................................................................. 32
8.8.2 Low-Frequency Ratio Configuration (LFRatioCfg) ................................................................ 32
8.9.1 Clock Input Bandwidth (ClkIn_BW[2:0]) ................................................................................ 32
23
CS
23
SysClk cycles .................................................................................. 15
SysClk cycles but > t
....................................................................................................... 15
CS
................................................................. 15
CS2000-CP
3