CS2000CP-DZZR Cirrus Logic Inc, CS2000CP-DZZR Datasheet - Page 14

• Manufacturer Part Number: CS2000CP-DZZR
• Description: IC General Purpose PLL Crystal
• Manufacturer: Cirrus Logic Inc
• Type: Fractional N Synthesizerr

Specifications of CS2000CP-DZZR

• Pll: Yes
• Input: Clock
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 2:2
• Differential - Input:output: No/No
• Frequency - Max: 75MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 3.1 V ~ 3.5 V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Frequency-max: 75MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1572 - KIT EVAL PROTOTYPING CS2300-CP598-1571 - KIT EVAL PROTOTYPING CS2000-CP598-1493 - BOARD EVAL GEN PURPOSE PLL DC598-1492 - BOARD EVAL GEN PURPOSE PLL DC598-1490 - BOARD EVAL GEN PURPOSE PLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 598-1400-2; CS2000CP-DZZR

14
5.1.3
5.2
5.2.1
5.2.2
Frequency Reference Clock Input, CLK_IN
The frequency reference clock input (CLK_IN) is used in Hybrid PLL Mode by the Digital PLL and Fractional-
N Logic block to dynamically generate a fractional-N value for the Frequency Synthesizer (see
alog-Digital PLL” on page
Fractional-N logic block then translates the desired ratio based off of CLK_IN to one based off of the internal
timing reference clock (SysClk). This allows the low-jitter timing reference clock to be used as the clock
which the Frequency Synthesizer multiplies while maintaining synchronicity with the frequency reference
clock through the Digital PLL. The allowable frequency range for CLK_IN is found in the
acteristics” on page
External Reference Clock (REF_CLK)
For operation with an externally generated REF_CLK signal, XTI/REF_CLK should be connected to the
reference clock source and XTO should be left unconnected or pulled low through a 47 kΩ resistor to
GND.
CLK_IN Frequency Detector
The CLK_IN frequency range detector determines and indicates the ratio between the frequency of the
internal SysClk and the CLK_IN input signal.
The result of the ratio measurement is available in the read-only FsDet[1:0] bits and is also used by the
device to determine the Auto R-Mod value.
Because f
ticularly useful when used in conjunction with the Auto R-Mod feature (see
CLK_IN Skipping Mode
CLK_IN skipping mode allows the PLL to maintain lock even when the CLK_IN signal has missing pulses
for up to
skipping mode can only be used when the CLK_IN frequency is below
this function.
Regardless of the setting of the ClkSkipEn bit the PLL output will continue for 2
to 1048 ms) after CLK_IN is removed (see
have an effective change in period as the clock source is removed, otherwise the PLL will interpret this as
a change in frequency causing clock skipping and the 2
PLL to immediately unlock. If the prior conditions are met while CLK_IN is removed and 2
pass, the PLL will unlock and the PLL_OUT state will be determined by the ClkOutUnl bit; See
Output” on page
Referenced Control
FsDet[1:0]..............................“PLL Input Sample Rate Indicator (FsDet[1:0]) - Read Only” section on page 27
20
SysClk
ms (t
is known, FsDet[1:0] can then be interpreted as a range for f
22. If CLK_IN is re-applied after such time, the PLL will remain unlocked for the specified
CS
8.
) at a time (see
FsDetect[1:0]
Register Location
12). The Digital PLL first compares the CLK_IN frequency to the PLL output. The
Table 1. PLL Input Clock Range Indicator
00
01
10
11
“AC Electrical Characteristics” on page 8
Figure
9). This is true as long as CLK_IN does not glitch or
f
SysClk
23
SysClk cycle time-out to be bypassed and the
Reserved
/ f
96 - 224
> 224
< 96
CLK_IN
80
Ratio
kHz. The ClkSkipEn bit enables
section 5.3.4 on page
for specifications). CLK_IN
CLK_IN
23
SysClk cycles (466 ms
. This feature is par-
“AC Electrical Char-
CS2000-CP
23
SysClk cycles
“Hybrid An-
DS761PP1
“PLL Clock
18)
.