CS2000CP-DZZR Cirrus Logic Inc, CS2000CP-DZZR Datasheet - Page 31

• Manufacturer Part Number: CS2000CP-DZZR
• Description: IC General Purpose PLL Crystal
• Manufacturer: Cirrus Logic Inc
• Type: Fractional N Synthesizerr

Specifications of CS2000CP-DZZR

• Pll: Yes
• Input: Clock
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 2:2
• Differential - Input:output: No/No
• Frequency - Max: 75MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 3.1 V ~ 3.5 V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Frequency-max: 75MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1572 - KIT EVAL PROTOTYPING CS2300-CP598-1571 - KIT EVAL PROTOTYPING CS2000-CP598-1493 - BOARD EVAL GEN PURPOSE PLL DC598-1492 - BOARD EVAL GEN PURPOSE PLL DC598-1490 - BOARD EVAL GEN PURPOSE PLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 598-1400-2; CS2000CP-DZZR

DS761PP1
8.7
8.7.1
8.7.2
8.7.3
ClkSkipEn
7
Function Configuration 1 (Address 16h)
Clock Skip Enable (ClkSkipEn)
This bit enables clock skipping mode for the PLL and allows the PLL to maintain lock even when the
CLK_IN has missing pulses.
Note:
AUX PLL Lock Output Configuration (AuxLockCfg)
When the AUX_OUT pin is configured as a lock indicator (AuxOutSrc[1:0] = 11), this bit configures the
AUX_OUT driver to either push-pull or open drain. It also determines the polarity of the lock signal. If
AUX_OUT is configured as a clock output, the state of this bit is disregarded.
Note:
fore, the pin polarity is defined relative to the unlock condition.
Reference Clock Input Divider (RefClkDiv[1:0])
Selects the input divider for the timing reference clock.
ClkSkipEn
0
1
Application:
AuxLockCfg
0
1
Application:
RefClkDiv[1:0]
00
01
10
11
Application:
AuxLockCfg
f
AUX_OUT is an unlock indicator, signalling an error condition when the PLL is unlocked. There-
CLK_IN
6
must be < 80 kHz to use this feature.
PLL Clock Skipping Mode
Disabled.
Enabled.
“CLK_IN Skipping Mode” on page 14
AUX_OUT Driver Configuration
Push-Pull, Active High (output ‘high’ for unlocked condition, ‘low’ for locked condition).
Open Drain, Active Low (output ‘low’ for unlocked condition, high-Z for locked condition).
“Auxiliary Output” on page 22
Reference Clock Input Divider
÷ 4.
÷ 2.
÷ 1.
Reserved.
“Internal Timing Reference Clock Divider” on page 13
Reserved
5
RefClkDiv1
4
RefClkDiv0
3
REF_CLK Frequency Range
32 MHz to 75 MHz (50 MHz with XTI)
16 MHz to 37.5 MHz
8 MHz to 18.75 MHz
Reserved
2
Reserved
1
CS2000-CP
Reserved
0
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