CS2000CP-DZZR Cirrus Logic Inc, CS2000CP-DZZR Datasheet - Page 16

• Manufacturer Part Number: CS2000CP-DZZR
• Description: IC General Purpose PLL Crystal
• Manufacturer: Cirrus Logic Inc
• Type: Fractional N Synthesizerr

Specifications of CS2000CP-DZZR

• Pll: Yes
• Input: Clock
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 2:2
• Differential - Input:output: No/No
• Frequency - Max: 75MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 3.1 V ~ 3.5 V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Frequency-max: 75MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1572 - KIT EVAL PROTOTYPING CS2300-CP598-1571 - KIT EVAL PROTOTYPING CS2000-CP598-1493 - BOARD EVAL GEN PURPOSE PLL DC598-1492 - BOARD EVAL GEN PURPOSE PLL DC598-1490 - BOARD EVAL GEN PURPOSE PLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 598-1400-2; CS2000CP-DZZR

16
5.2.3
SDATA
SDATA
Adjusting the Minimum Loop Bandwidth for CLK_IN
The CS2000 allows the minimum loop bandwidth of the Digital PLL to be adjusted between 1 Hz and 128
Hz using the ClkIn_BW[2:0] bits. The minimum loop bandwidth of the Digital PLL directly affects the jitter
transfer function; specifically, jitter frequencies below the loop bandwidth corner are passed from the PLL
input directly to the PLL output without attenuation. In some applications it is desirable to have a very low
minimum loop bandwidth to reject very low jitter frequencies, commonly referred to as wander. In others
it may be preferable to remove only higher frequency jitter, allowing the input wander to pass through the
PLL without attenuation.
Typically, applications in which the PLL_OUT signal creates a new clock domain from which all other sys-
tem clocks and associated data are derived will benefit from the maximum jitter and wander rejection of
the lowest PLL bandwidth setting. See
Systems in which some clocks and data are derived from the PLL_OUT signal while other clocks and data
are derived from the CLK_IN signal will often require phase alignment of all the clocks and data in the
system. See
be necessary to increase the minimum loop bandwidth allowing this wander to pass through to the
CLK_OUT signal in order to maintain phase alignment. For these applications, it is advised to experiment
with the loop bandwidth settings and choose the lowest bandwidth setting that does not produce system
timing errors due to wandering between the clocks and data synchronous to the CLK_IN domain and
those synchronous to the PLL_OUT domain.
It should be noted that manual adjustment of the minimum loop bandwidth is not necessary to acquire
lock; this adjustment is made automatically by the Digital PLL. While acquiring lock, the digital loop band-
width is automatically set to a large value. Once lock is achieved, the digital loop bandwidth will settle to
the minimum value selected by the ClkIn_BW[2:0] bits.
MCLK
LRCK
SCLK
Referenced Control
ClkIn_BW[2:0]
MCLK
LRCK
SCLK
Wander < 128 Hz
Wander > 1 Hz
.......................“Clock Input Bandwidth (ClkIn_BW[2:0])” on page 32
Figure
D0
D0
Figure 13. High bandwidth with CLK_IN domain re-use
13. If there is substantial wander on the CLK_IN signal in these applications, it may
Figure 12. Low bandwidth and new clock domain
Jitter
Jitter
Register Location
D1
D1
CLK_IN
CLK_IN
or
or
BW = 128 Hz
Figure
BW = 1 Hz
PLL
Subclocks and data re-used
from previous clock domain.
PLL
12.
from new clock domain.
Subclocks generated
PLL_OUT
PLL_OUT
Wander < 128 Hz Passed to Output
SDATA
SDATA
Wander and Jitter > 1 Hz Rejected
MCLK
LRCK
SCLK
MCLK
LRCK
SCLK
Jitter > 128 Hz Rejected
D0
CS2000-CP
D0
DS761PP1
D1
D1