CS4299-JQZR Cirrus Logic Inc, CS4299-JQZR Datasheet - Page 33

• Manufacturer Part Number: CS4299-JQZR
• Description: IC AC97 Codec With SRC
• Manufacturer: Cirrus Logic Inc
• Series: SoundFusion™r
• Type: Audio Codec '97r

Specifications of CS4299-JQZR

• Data Interface: Serial
• Resolution (bits): 18 b, 20 b
• Number Of Adcs / Dacs: 1 / 1
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 85 / 87
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 3.3 V ~ 5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• No. Of Dacs: 1
• No. Of Input Channels: 6
• No. Of Output Channels: 2
• Adc / Dac Resolution: 20bit
• Adcs / Dacs Signal To Noise Ratio: 70dB
• Sampling Rate: 48kSPS
• Supply Voltage Range: 3.135V To 3.465V, 4.75V To 5.25V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS319PP6
5. POWER MANAGEMENT
5.1
The CS4299 supports three reset methods, as de-
fined in the AC ’97 Specification: Cold AC ’97 Re-
set, Warm AC ’97 Reset, Register AC ’97 Reset. A
Cold Reset results in all AC ’97 logic (registers in-
cluded) initialized to its default state. A Warm Re-
set leaves the contents of the AC ’97 register set
unaltered. A Register Reset initializes only the
AC ’97 registers to their default states.
5.1.1
A Cold Reset is achieved by asserting RESET# for
a minimum of 1 µs after the power supply rails
have stabilized. This is done in accordance with the
minimum timing specifications in the AC ’97 Seri-
al Port Timing section on page 7. Once deasserted,
all of the CS4299 registers will be reset to their de-
fault power-on states and the BIT_CLK and
SDATA_IN signals will be reactivated.
AC ’97 Reset Modes
Cold AC ‘97 Reset
5.1.2
A Warm Reset allows the AC-link to be reactivated
without losing information in the CS4299 registers.
A Warm Reset is required to resume from a D3
state, where the AC-link had been halted yet full
power had been maintained. A primary codec
Warm Reset is initiated when the SYNC signal is
driven high for at least 1 µs and then driven low in
the absence of the BIT_CLK clock signal. The
BIT_CLK clock will not restart until at least 2 nor-
mal BIT_CLK clock periods (162.8 ns) after the
SYNC signal is deasserted. A Warm Reset of the
secondary codec is recognized when the primary
codec on the AC-link resumes BIT_CLK genera-
tion. The CS4299 will wait for BIT_CLK to be sta-
ble to restore SDATA_IN activity and/or S/PDIF
transmission on the following frame.
5.1.3
The third reset mode provides a Register Reset to
the CS4299. This is available only when the
CS4299 AC-link is active and the Codec Ready bit
is ‘set’. The audio (including extended audio) reg-
isters (Index 00h - 38h) and the vendor specific reg-
isters (Index 5Ah - 7Ah) are reset to their default
states by a write of any value to the Reset Register
(Index 00h).
Warm AC ’97 Reset
Register AC ’97 Reset
CS4299
CS4299
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