CS4299-JQZR Cirrus Logic Inc, CS4299-JQZR Datasheet - Page 7
![IC AC97 Codec With SRC](/photos/40/58/405889/4784370_sml.jpg)
CS4299-JQZR
Manufacturer Part Number
CS4299-JQZR
Description
IC AC97 Codec With SRC
Manufacturer
Cirrus Logic Inc
Series
SoundFusion™r
Type
Audio Codec '97r
Datasheet
1.CS4299-JQZ.pdf
(52 pages)
Specifications of CS4299-JQZR
Data Interface
Serial
Resolution (bits)
18 b, 20 b
Number Of Adcs / Dacs
1 / 1
Sigma Delta
Yes
Dynamic Range, Adcs / Dacs (db) Typ
85 / 87
Voltage - Supply, Analog
4.75 V ~ 5.25 V
Voltage - Supply, Digital
3.3 V ~ 5 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
48-LQFP
No. Of Dacs
1
No. Of Input Channels
6
No. Of Output Channels
2
Adc / Dac Resolution
20bit
Adcs / Dacs Signal To Noise Ratio
70dB
Sampling Rate
48kSPS
Supply Voltage Range
3.135V To 3.465V, 4.75V To 5.25V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CS4299-JQZR
Manufacturer:
ON
Quantity:
2 245
Company:
Part Number:
CS4299-JQZR
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
DS319PP6
AC ’97 SERIAL PORT TIMING
AVdd = 5.0 V, DVdd = 3.3 V; C
RESET Timing
RESET# active low pulse width
RESET# inactive to BIT_CLK start-up delay
1st SYNC active to CODEC READY set
Vdd stable to Reset inactive
Clocks
BIT_CLK frequency
BIT_CLK period
BIT_CLK output jitter (depends on XTAL_IN source)
BIT_CLK high pulse width
BIT_CLK low pulse width
SYNC frequency
SYNC period
SYNC high pulse width
SYNC low pulse width
Data Setup and Hold
Output Propagation delay from rising edge of BIT_CLK
Input setup time from falling edge of BIT_CLK
Input hold time from falling edge of BIT_CLK
Input Signal rise time
Input Signal fall time
Output Signal rise time
Output Signal fall time
Misc. Timing Parameters
End of Slot 2 to BIT_CLK, SDATA_IN low (PR4)
SYNC pulse width (PR4) Warm Reset
SYNC inactive (PR4) to BIT_CLK start-up delay
Setup to trailing edge of RESET# (ATE test mode) (Note 4) T
Rising edge of RESET# to Hi-Z delay
Parameter
L
= 55 pF load.
Standard test conditions unless otherwise noted: T
(Note 4)
(Note 4)
(Note 4)
T
T
T
T
sync_period
T
T
T
T
Symbol
T
T
T
clk_period
T
sync_high
s2_pdown
T
sync2crd
sync_low
T
sync_pr4
setup2rst
vdd2rst#
sync2clk
clk_high
F
T
T
clk_low
T
T
rst_low
rst2clk
T
F
isetup
T
T
orise
sync
ihold
irise
ofall
ifall
clk
co
off
162.8
Min
100
1.0
1.0
36
36
10
15
8
0
2
2
2
2
-
-
-
-
-
-
-
-
-
-
-
12.288
40.0
62.5
81.4
20.8
19.5
40.7
40.7
Typ
285
1.3
.28
48
10
4
4
-
-
-
-
-
-
-
-
-
-
ambient
Max
750
1.0
45
45
12
25
6
6
6
6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
CS4299
= 25° C,
CS4299
MHz
Unit
kHz
µs
µs
µs
µs
µs
µs
µs
µs
µs
ns
ps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7
7