CS42L52-CNZR Cirrus Logic Inc, CS42L52-CNZR Datasheet - Page 49

• Manufacturer Part Number: CS42L52-CNZR
• Description: IC,Soundcard Circuits,LLCC,40PIN,PLASTIC
• Manufacturer: Cirrus Logic Inc
• Type: Stereo Audior

Specifications of CS42L52-CNZR

• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 1 / 1
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 99 / 98
• Voltage - Supply, Analog: 1.65 V ~ 2.63 V
• Voltage - Supply, Digital: 1.65 V ~ 2.63 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 40-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1580 - REFERENCE DESIGN FOR CS42L52598-1508 - BOARD EVAL FOR 42LDB1 CODEC598-1505 - BOARD EVAL FOR CS42L52 CODEC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS680F1
6.8.2
6.9
6.9.1
6.9.2
6.9.3
6.9.4
HPFB
7
Analog & HPF Control (Address 0Ah)
PGA Input Mapping
Selects one or sums/mixes the analog input signal into the PGA. Each bit of the PGAx_SEL[5:1] word
corresponds to individual channels (i.e. PGAx_SEL1 selects AIN1x, PGAx_SEL2 selects AIN2x, etc.).
ADCx High-Pass Filter
Configures the internal high-pass filter after ADCx.
ADCx High-Pass Filter Freeze
Configures the high pass filter’s digital DC subtraction and/or calibration after ADCx.
Ch. x Analog Soft Ramp
Configures an incremental volume ramp from the current level to the new level at the specified rate.
Ch. x Analog Zero Cross
Configures when the signal level changes occur for the analog volume controls.
Note:
timeout period of 1024 sample periods (approximately 10.7 ms at 48 kHz sample rate).
PGAxSEL[5:1]
00000
00001
00010
00100
01000
10000
10001
10011
Application:
Note: Table does not show all possible combinations.
HPFx
0
1
HPFRZx
0
1
ANLGSFTx
0
1
Ramp Rate:
ANLGZCx
0
1
HPFRZB
If the signal does not encounter a zero crossing, the requested volume change will occur after a
6
Selected Input to PGAx (Examples)
No inputs selected
AIN1x
AIN2x
AIN3x
AIN4x
MICx; for single-ended MIC inputs, use MICxSEL (
differential MIC inputs, enable MICxCFG (
MICx + AIN1x
MICx + AIN1x + AIN2x
“Analog Inputs” on page 26
High Pass Filter Status
Disabled
Enabled
High Pass Filter Digital Subtraction
Continuous DC Subtraction
Frozen DC Subtraction
Volume Changes
Do not occur with a soft ramp
Occur with a soft ramp
1/2 dB every 16 LRCK cycles
Volume Changes
Do not occur on a zero cross-
ing
Occur on a zero crossing
HPFA
5
HPFRZA
4
Affected Analog Volume Controls
MICxGAIN[4:0]
on page
Affected Analog Volume Controls
MICxGAIN[4:0]
on page
5/13/08
ANLGSFTB
56), and PASSxVOL[7:0]
56), and PASSxVOL[7:0]
“MICx Configuration” on page 55
3
(“MICx Gain” on page
(“MICx Gain” on page
“MIC x Select” on page 55
ANLGZCB
2
(“Passthrough x Volume” on page
(“Passthrough x Volume” on page
55), PGAxVOL[5:0]
55), PGAxVOL[5:0]
)
ANLGSFTA
) to select MIC 1 or MIC 2; for
1
(“PGAx Volume”
(“PGAx Volume”
CS42L52
ANLGZCA
0
57)
57)
49