CS43L22-CNZR Cirrus Logic Inc, CS43L22-CNZR Datasheet - Page 38

• Manufacturer Part Number: CS43L22-CNZR
• Description: IC Low Power DAC W/ClassD Spkr Driver
• Manufacturer: Cirrus Logic Inc

Specifications of CS43L22-CNZR

• Number Of Bits: 24
• Data Interface: Serial
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1529 - BOARD EVAL FOR CS43L22
• Power Dissipation (max): -
• Settling Time: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

38
7.3
7.3.1
7.3.2
7.4
7.4.1
PDN_HPB1
AUTO
7
7
Power Control 2 (Address 04h)
Clocking Control (Address 05h)
Headphone Power Control
Configures how the SPK/HP_SW pin, 6, controls the power for the headphone amplifier.
Speaker Power Control
Configures how the SPK/HP_SW pin, 6, controls the power for the speaker amplifier.
Auto-Detect
Configures the auto-detect circuitry for detecting the speed mode of the CS43L22 when operating as a
slave.
Notes:
1. The SPEED[1:0] bits are ignored and speed is determined by the MCLK/LRCK ratio.
2. When AUTO is disabled and the CS43L22 operates in Master Mode, the MCLKDIV2 bit is ignored.
3. Certain sample and MCLK frequencies require setting the SPEED[1:0] bits, the 32k_GROUP bit
PDN_HPx[1:0]
00
01
10
11
PDN_SPKx[1:0]
00
01
10
11
AUTO
0
1
Application:
(“32kHz Sample Rate Group” on page
page
affect dynamic range performance in the typical audio band. Refer to the referenced application for
more information.
PDN_HPB0
SPEED1
39) and RATIO[1:0] bits
6
6
Headphone Status
Headphone channel is ON when the SPK/HP_SW pin, 6, is LO.
Headphone channel is OFF when the SPK/HP_SW pin, 6, is HI.
Headphone channel is ON when the SPK/HP_SW pin, 6, is HI.
Headphone channel is OFF when the SPK/HP_SW pin, 6, is LO.
Headphone channel is always ON.
Headphone channel is always OFF.
Speaker Status
Speaker channel is ON when the SPK/HP_SW pin, 6, is LO.
Speaker channel is OFF when the SPK/HP_SW pin, 6, is HI.
Speaker channel is ON when the SPK/HP_SW pin, 6, is HI.
Speaker channel is OFF when the SPK/HP_SW pin, 6, is LO.
Speaker channel is always ON.
Speaker channel is always OFF.
Auto-detection of Speed Mode
Disabled
Enabled
“Serial Port Clocking” on page 29
PDN_HPA1
SPEED0
5
5
(“Internal MCLK/LRCK Ratio” on page
32k_GROUP
PDN_HPA0
Confidential Draft
4
4
39) and/or the VIDEOCLK bit
3/4/10
PDN_SPKB1
VIDEOCLK
3
3
PDN_SPKB0
RATIO1
2
2
39). Low sample rates may also
(“27 MHz Video Clock” on
PDN_SPKA1
RATIO0
1
1
CS43L22
PDN_SPKA0
MCLKDIV2
DS792F2
0
0