CS43L22-CNZR Cirrus Logic Inc, CS43L22-CNZR Datasheet - Page 55

• Manufacturer Part Number: CS43L22-CNZR
• Description: IC Low Power DAC W/ClassD Spkr Driver
• Manufacturer: Cirrus Logic Inc

Specifications of CS43L22-CNZR

• Number Of Bits: 24
• Data Interface: Serial
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1529 - BOARD EVAL FOR CS43L22
• Power Dissipation (max): -
• Settling Time: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS792F2
7.25
7.25.1 Limiter Attack Rate
7.26
7.26.1 Serial Port Clock Error (Read Only)
7.26.2 DSP Engine Overflow (Read Only)
Reserved
Reserved
7
7
Limiter Attack Rate (Address 29h)
Status (Address 2Eh) (Read Only)
For all bits in this register, a “1” means the associated error condition has occurred at least once since the
register was last read. A”0” means the associated error condition has NOT occurred since the last reading
of the register. Reading the register resets all bits to 0.
Sets the rate at which the limiter applies digital attenuation from levels above the MAX[2:0] threshold
(“Limiter Maximum Threshold” on page
Note:
the DIGSFT
the respective disable bit
page
Indicates the status of the MCLK to LRCK ratio.
Note:
nizes.
Indicates the over-range status in the DSP data path.
LIMARATE[5:0]
00 0000
···
11 1111
Application:
SPCLKERR
0
1
Application:
DSPxOVFL
0
1
Application:
54) is enabled.
SPCLKERR
Reserved
The limiter attack rate is user-selectable but is also a function of the sampling frequency, Fs, and
On initial power up and application of clocks, this bit will report ‘1’b as the serial port re-synchro-
6
6
(“Digital Soft Ramp” on page
Attack Time
Fastest Attack
···
Slowest Attack
“Limiter” on page 22
Serial Port Clock Status:
MCLK/LRCK ratio is valid.
MCLK/LRCK ratio is not valid.
“Serial Port Clocking” on page 29
DSP Overflow Status:
No digital clipping has occurred in the data path after the DSP.
Digital clipping has occurred in the data path after the DSP.
“DSP Engine” on page 21
LIMARATE5
DSPAOVFL
5
5
(“Limiter Soft Ramp Disable” on page 53
LIMARATE4
DSPBOVFL
Confidential Draft
4
4
53).
44) and DIGZC
3/4/10
LIMARATE3
PCMAOVFL
3
3
(“Digital Zero Cross” on page
PCMBOVFL
LIMARATE2
2
2
or
“Limiter Zero Cross Disable” on
LIMARATE1
Reserved
1
1
45) setting unless
CS43L22
LIMARATE0
Reserved
0
0
55